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broadband modem mixed signal front end ad9866 rev. 0 in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2003 analog de vices, i n c. al l r i ght s r e ser v ed . fea t ures l o w c o st 3.3 v cmos mxfe tm f o r br oadband modems 12-bit d/a c o n v er t e r 2/4 int e rpola t ion filt er 200 msps d a c upda t e r a t e int e gr a t ed 23 dbm line dri v er with 19.5 db g a in c o ntrol 12-bit , 80 msp s a/d c o n v er te r ?12 db to +48 db low no ise rxpga (< 2.5 nv /r thz) t h ir d or der pr ogr a mmable lo w - pass filt er f l e x ible digita l da ta pa th in t e r f ac e half- and f u ll - d uple x oper a t ion backward c o mpa t ible with a d 9975 and ad 9876 v a rious pow e r- down/r educ tion modes in t e rnal clock mu ltiplier (pll) 2 auxili ar y pr ogr a mmable clock outputs a v ai lable in 64 -lead chip sc ale pack age or bar e die a pplic a t io ns p o w e rline net w ork i ng vdsl and hpn a func ti onal bl oc k di a g ram 12 xt a l rx ? 4 6 ad986 6 12 0 to ? 7.5db 04560-0-001 0 to ?12db register control clk syn. adc 80msps 2-4x iou t _ g + iou t _ n + iou t _ n ? iou t _ g ? cl ko ut _ 1 cl ko ut _ 2 os c i n rx + iamp txdac iou t _p+ iou t _p ? 2 m clk multiplier 2-pole lpf 1-pole lpf 0 to 6db ? = 1db ? 6 to 18db ? = 6db ?6 to 24db ? = 6db spi ag c[ 5 : 0] rx cl k r xe/ syn c a d i o [ 1 1 :6 ]/ t x [5 :0 ] a d io [5 :0 ]/ r x [5 :0 ] tx c l k t xen /syn c mo de pw r d w n fi g u r e 1 . gener a l de scription the ad9866 is a mixed-sig n al f r o n t en d (mxfe) i c f o r t r a n s c ei v e r a p pl ica t ion s r e q u ir i n g tx and rx p a t h f u n c t i o n a l i t y w i t h da t a r a te s up to 8 0 m s p s . i t s f l e x ibl e di g i t a l i n te r f a c e, p o w e r s a v i n g mo des, a nd hig h tx -to - rx is ola t i o n ma k e i t w e l l s u i t e d f o r half- a nd f u l l -d u p lex a p p l ic a t ion s . the dig i tal in t e r - face is ext r eme l y f l exi b le al lo wi ng s i m p l e i n te r f a c e s to di g i t a l bac k e n ds tha t su p p o r t half- o r f u l l -d u p lex da t a tra n sfers, th us o f t e n al lo win g t h e ad9866 t o rep l ace dis c r e t e ad c and d a c so l u ti o n s . p o w e r sa v i n g m o d e s i n c l u d e t h e a b il i t y t o r e d u c e p o we r c o nsu m pt i o n of i n d i v i d u a l f u nc t i on a l bl o c k s or to p o we r do wn u n us e d b l o c ks in half-d u p lex a p p l ica t io ns. a s e r i al p o r t in t e r f ace (spi?) a l lo ws s o f t wa r e p r og ra mmin g of t h e va r i o u s fun c ti o n al b l ock s . a n o n - c hi p p ll c l oc k m u l t i p li er a n d sy n t h e si zer p r o v ide a l l t h e r e q u ir e d i n t e r n a l clo c ks, as w e l l as tw o ext e r n a l clo c ks f r o m a sin g l e cr y s t a l o r clo c k s o ur ce. the tx sig n al p a th con s is ts o f a b y p a s s a b le 2/4 lo w-p a s s in t e r p ol a t ion f i lt er , a 12-b i t txd a c, an d a li n e dr i v er . th e t r a n smi t p a t h si g n a l b a n d wi d t h ca n b e as hig h as 34 mhz a t a n in p u t da t a ra te o f 80 ms ps. the txd a c p r o v i d es dif f er en t i al cu rr e n t o u t p u t s th a t ca n be s t eer ed d i r e ctl y t o a n e x t e rn al l o a d or to an i n te r n a l l o w d i stor t i on c u r r e n t am pl i f i e r . t h e c u r r e n t a m plif ier (i am p) ca n b e conf igur e d as a c u r r en t o r v o l t a g e m o de lin e dr i v er (wi t h tw o ext e r n al n p n tra n sist o r s) ca p a b l e o f de li v e r i n g in exces s o f 23 db m p e ak sig n al p o w e r . tx p o w e r ca n be dig i t a l l y co n t r o l l ed o v er a 19.5 db ra n g e in 0. 5 db s t eps. the r e cei v e p a t h co n s is ts o f a pr og ra mma b l e a m plif ier (rxpga), a t u na b l e lo w p a s s f i l t er (lp f ), a nd a 12-b i t ad c. the lo w n o is e rxpg a has a p r og ramma b l e ga i n ran g e o f ?12 db to +48 db in 1 db st eps. i t s in p u t refer r e d n o is e is less t h a n 3.3 nv/r th z f o r ga in s e t t in gs b e yo n d 30 db . the r e cei v e p a t h lp f c u t o f f f r eq uen c y can ei t h er be s e t o v er a 1 5 mh z t o 35 mh z ra n g e or sim p l y b y p a s s ed . th e 12 -b i t ad c ac hiev es exce l l en t d y namic p e r f o r ma n c e o v er a 5 ms ps t o 80 ms ps s p a n . b o th t h e r x pga a n d th e a d c o f f e r scala b le po w e r c o nsu m pt i o n a l l o w i ng p o we r / p e r f o r m a nc e opt i m i z a t i o n . the ad9866 p r o v ides a hig h l y in t e g r a t e d s o l u tio n f o r ma n y b r o a d b and m o d e m s . i t is a v ai lab l e in a sp ace - s a vin g 64 -le a d chi p s c ale p a ckag e a nd is sp e c if i e d o v er t h e comm er c i al (?40c to + 8 5 c ) te m p e r a t u r e r a ng e.
ad9866 rev. 0 | page 2 of 48 table of contents specifications ..................................................................................... 3 tx path specifications .................................................................. 3 rx path specifications .................................................................. 4 power supply specifications ....................................................... 5 digital specifications ................................................................... 6 serial port timing specifications ............................................... 7 half-duplex data interface (adio port) timing specifications ................................................................................ 7 full-duplex data interface (tx and rx port) timing specifications ................................................................................ 8 absolute maximum ratings ............................................................ 9 thermal characteristics .............................................................. 9 esd caution .................................................................................. 9 pin configuration and function descriptions ........................... 10 typical performance characteristics ........................................... 12 rx path typical performance characteristics ........................ 12 txdac path typical performance characteristics ............... 16 iamp path typical performance characteristics .................. 18 serial port ........................................................................................ 19 register map description ......................................................... 21 serial port interface (spi) ......................................................... 21 digital interface .............................................................................. 23 half-duplex mode ..................................................................... 23 full-duplex mode ...................................................................... 24 rxpga control .......................................................................... 25 txpga control .......................................................................... 27 transmit path .................................................................................. 28 digital interpolation filters ...................................................... 28 txdac and iamp architecture ............................................... 28 tx programmable gain control .............................................. 30 txdac output operation ........................................................ 30 iamp current mode operation .............................................. 30 iamp voltage mode operation ............................................... 31 iamp current consumption considerations ........................ 32 receive path .................................................................................... 33 rx programmable gain amplifier ........................................... 33 low-pass filter ........................................................................... 34 analog to digital converter (adc) ........................................ 35 agc timing considerations .................................................... 36 clock synthesizer ........................................................................... 37 power control and dissipation .................................................... 39 power-down ............................................................................... 39 half-duplex power savings ...................................................... 39 power reduction options ......................................................... 40 power dissipation ...................................................................... 42 mode select upon power-up and reset .................................. 42 analog and digital loop-back test modes ............................ 43 pcb design considerations .......................................................... 44 component placement .............................................................. 44 power planes and decoupling .................................................. 44 ground planes ............................................................................ 44 signal routing ............................................................................ 44 evaluation board ............................................................................ 46 outline dimensions ....................................................................... 47 ordering guide .......................................................................... 47 revision history revision 0: initial version
ad9866 rev. 0 | page 3 of 48 specifications tx path specifications table 1. avdd = 3.3 v 5%, dvdd = clkvdd = drvdd = 3.3 v 10%; f oscin = 50 mhz, f dac = 200 mhz, r set = 2.0 k?, unless otherwise noted parameter temp test level min typ max unit txdac dc characteristics resolution full 12 bits update rate full ii 200 msps full-scale output current (ioutp_fs) full iv 2 25 ma gain error 1 25c i 2 % fs offset error 25c v 2 ua voltage compliance range full ?1 +1.5 v txdac gain control characteristics minimum gain 25c v ?7.5 db maximum gain 25c v 0 db gain step size 25c v 0.5 db gain step accuracy 25c iv monotonic gain range error 25c v 2 db txdac ac characteristics 2 fundamental 0.5 dbm signal-to-noise and distortion full iv 66.6 69.2 dbc signal-to-noise ratio full iv 68.4 69.8 dbc thd full iv ?79 ?68.7 dbc sfdr full iv 68.5 81 dbc iamp dc characteristics ioutn full-scale current = ioutn+ + ioutn? full iv 2 105 ma ioutg full-scale current = ioutg+ + ioutg? full iv 2 150 ma ac voltage compliance range full iv 1 7 v iampn ac characteristics 3 fundamental 25c 13 dbm ioutn sfdr (third harmonic) full iv 43.3 45.2 dbc iamp gain control characteristics minimum gain 25c v ?19.5 db maximum gain 25c v 0 db gain step size 25c v 0.5 db gain step accuracy 25c iv monotonic db ioutn gain range error 25c v 0.5 db reference internal reference voltage 4 25c i 1.23 v reference error full v 0.7 3.4 % reference drift full v 30 ppm/ o c tx digital filter characteristics (2 interpolation) latency (relative to 1/ f dac ) full v 43 cycles ?0.2 db bandwidth full v 0.2187 f out /f dac ?3 db bandwidth full v 0.2405 f out /f dac stop-band rejection (0.289 f dac to 0.711 f dac ) full v 50 db tx digital filter characteristics (4 interpolation) latency (relative to 1/ f dac ) full v 96 cycles ?0.2 db bandwidth full v 0.1095 f out /f dac
ad9866 rev. 0 | page 4 of 48 parameter temp test level min typ max unit ?3 db bandwidth full v 0.1202 f out /f dac stop band rejection (0.289 f oscin to 0.711 f oscin ) full v 50 db pll clk multiplier oscin frequency range full iv 5 80 mhz internal vco frequency range full iv 20 200 mhz duty cycle full ii 40 60 % oscin impedance 25c v 100//3 ?//pf clkout1 jitter 5 25c iii 12 ps rms clkout2 jitter 6 25c iii 6 ps rms clkout1 and clkout2 duty cycle 7 full iii 45 55 % 1 gain error and gain temperature coefficients are based on the adc only (with a fixed 1.23 v external reference and a 1 v p-p d ifferential analog input). 2 txdac ioutfs = 20 ma, differential output with 1:1 transformer with source and load termination of 50 ?, f out = 5 mhz, 4 interpolation. 3 ioun full-scale current = 80 ma, f oscin = 80 mhz, f dac =160 mhz, 2 interpolation. 4 use external amplifier to drive additional load. 5 internal vco operates at 200 mhz , set to divide-by - 1. 6 because clkout2 is a divided down version of oscin, its jitter is typically equal to oscin. 7 clkout2 is an inverted replica of oscin, if set to divide-by-1. rx path specifications table 2. avdd = 3.3 v 5%, dvdd = clkvdd = drvdd = 3.3 v 10%; half- or full-duplex operation with config = 0 default power bias settings, unless otherwise noted parameter temp test level min typ max unit rx input characteristics input voltage span (rxpga gain = ?10 db) full iii 6.33 v p-p input voltage span (rxpga gain = +48 db) full iii 8 mv p-p input common-mode voltage 25c iii 1.3 v differential input impedance 25c iii 400 4.0 ? pf input bandwidth (with rxlpf disabled, rxpga = 0 db) 25c iii 53 mhz input voltage noise density (rxpga gain = 36 db, f ?3 dbf = 26 mhz) 25c iii 2.7 nv/rthz input voltage noise density (rxpga gain = 48 db, f ?3 dbf = 26 mhz) 25c iii 2.4 nv/rthz rxpga characteristics minimum gain 25c iii ?12 db maximum gain 25c iii 48 db gain step size 25c iii 1 db gain step accuracy 25c iii monotonic db gain range error 25c iii 0.5 db rxlpf characteristics cutoff frequency (f ?3 dbf ) range full iii 15 35 mhz attenuation at 55.2 mhz with f ?3 dbf = 21 mhz 25c iii 20 db pass-band ripple 25c iii 1 db settling time to 5 db rxpga gain step @ f adc = 50 msps 25c iii 20 ns settling time to 60 db rxpga gain step @ f adc = 50 msps 25c iii 100 ns adc dc characteristics resolution na na 12 bits conversion rate full ii 5 80 msps rx path latency 1 full-duplex interface full v 10.5 cycles half-duplex interface full v 10.0 cycles
ad9866 rev. 0 | page 5 of 48 parameter temp test level min typ max unit rx path composite ac performance @ f adc = 50 msps 2 rxpga gain = 48 db (full-scale = 8.0 mv p-p) signal-to-noise and distortion (snr) 25c iii 43.7 dbc total harmonic distortion (thd) 25c iii ?71 dbc rxpga gain = 24 db (full-scale = 126 mv p-p) signal-to-noise (snr) 25c iii 63.1 dbc total harmonic distortion (thd) 25c iii ?67.2 dbc rxpga gain = 0 db (full-scale = 2.0 v p-p) signal-to-noise and distortion (sinad) full iv 64.3 dbc total harmonic distortion (thd) full iv ?67.3 dbc rx path composite ac performance @ f adc = 80 msps 3 rxpga gain = 48 db (full-scale = 8.0 m v p-p) signal-to-noise (snr) 25c iii 41.8 dbc total harmonic distortion (thd) 25c iii ?67 dbc rxpga gain = 24 db (full-scale = 126 m v p-p) signal-to-noise (snr) 25c iii 58.6 dbc total harmonic distortion (thd) 25c iii ?62.9 dbc rxpga gain = 0 db (full-scale = 2.0 v p-p) signal-to-noise (snr) 25c ii 61.1 62.9 dbc total harmonic distortion (thd) 25c ii ?70.8 ?60.8 dbc rx-to-tx path full-duplex isolation (1 v p-p, 10 mhz sine wave tx output) rxpga gain = 40 db ioutp pins to rx pins 25c iii 83 dbc ioutg pins to rx pins 25c iii 37 dbc rxpga gain = 0 db ioutp pins to rx pins 25c iii 123 dbc ioutg pins to rx pins 25c iii 77 dbc 1 includes rxpga, adc pipeline, and adio bus delay relative to f adc . 2 f in = 5 mhz, ain = ?1.0 dbfs , lpf cut-off frequency set to 15.5 mhz with reg. 0x08 = 0x80. 3 f in = 5 mhz, ain = ?1.0 dbfs , lpf cut-off frequency set to 26 mhz with reg. 0x08 = 0x80. power supply specifications table 3. avdd = 3.3 v, dvdd = clkvdd = drvdd = 3.3 v; r set = 2 k?, full-duplex operation with f data = 80 msps, 1 unless otherwise noted parameter temp test level min typ max unit supply voltages avdd full v 3.135 3.3 3.465 v clkvdd full v 3.0 3.3 3.6 v dvdd full v 3.0 3.3 3.6 v drvdd full v 3.0 3.3 3.6 v is_total (total supply current) full ii 406 475 ma power consumption i avdd + i clkvdd (analog supply current) iv 311 342 ma i dvdd + i drvdd (digital supply current) full iv 95 133 ma power consumption (half-du plex operation with f data = 50 msps) 2 tx mode i avdd + i clkvdd 25c iv 112 130 ma i dvdd + i drvdd 25c iv 46 49.5 ma
ad9866 rev. 0 | page 6 of 48 parameter temp test level min typ max unit rx mode i avdd + i clkvdd 25c 225 253 ma i dvdd + i drvdd 25c 36.5 39 ma power consumption of functional blocks 1 (i avdd + i clkvdd ) rxpga and lpf 25c iii 87 ma adc 25c iii 108 ma txdac 25c iii 38 ma iamp (programmable) 25c iii 10 120 ma reference 25c iii 170 ma clk pll and synthesizer 25c iii 107 ma maximum allowable power dissipation full iv 1.66 w standby power consumption is_total (total supply current) full 13 ma power down delay (using pwr_dwn pin) rxpga and lpf 25c iii 440 ns adc 25c iii 12 ns txdac 25c iii 20 ns iamp 25c iii 20 ns clk pll and synthesizer 25c iii 27 ns power up delay (using pwr_dwn pin) rxpga and lpf 25c iii 7.8 s adc 25c iii 88 ns txdac 25c iii 13 s iamp 25c iii 20 ns clk pll and synthesizer 25c iii 20 s 1 default power-up settings for mode = high and config = low, ioutp_fs = 20 ma, does not include iamps current consumption, whic h is application dependent. 2 default power-up settings for mode = low and config = low . digital specifications table 4. avdd = 3.3 v 5%, dvdd = clkvdd = drvdd = 3.3 v 10%; r set = 2 k?, unless otherwise noted parameter temp test level min typ max unit cmos logic inputs high level input voltage full vi drvdd C 0.7 v low level input voltage full vi 0.4 v input leakage current 12 a input capacitance full vi 3 pf cmos logic outputs (c load = 5 pf) high level output voltage (i oh = 1 ma) full vi drvdd C 0.7 low level output voltage (i oh = 1 ma) full vi 1.2 2 output rise/fall time (high strength mode and c load = 15 pf) full vi 1.5/2.3 ns output rise/fall time (low strength mode and c load = 15 pf) full vi 1.9/2.7 ns output rise/fall time (high strength mode and c load = 5 pf) full vi 0.7/0.7 ns output rise/fall time (low strength mode and c load = 5 pf) full vi 1.0/1.0 ns reset minimum low pulse width (relative to f adc ) 1 clock cycles
ad9866 rev. 0 | page 7 of 48 serial port timing specifications table 5. avdd = 3.3 v 5%, dvdd = clkvdd = drvdd = 3.3 v 10%, unless otherwise noted parameter temp test level min typ max unit write operation (see figure 46) sclk clock rate (f sclk ) full iv 32 mhz sclk clock high (t hi ) full iv 14 ns sclk clock low (t low ) full iv 14 ns sdio to sclk setup time (t ds ) full iv 14 ns sclk to sdio hold time (t dh ) full iv 0 ns sen to sclk setup time (t s ) full iv 14 ns sclk to sen hold time (t h ) full iv 0 ns read operation (see figure 47 and figure 48) sclk clock rate (f sclk ) full iv 32 mhz sclk clock high (t hi ) full iv 14 ns sclk clock low (t low ) full iv 14 ns sdio to sclk setup time (t ds ) full iv 14 ns sclk to sdio hold time (t dh ) full iv 0 ns sclk to sdio (or sdo) data valid time (t dv ) full iv 14 ns sen to sdio output valid to hi-z (t ez ) full iv 2 ns half-duplex data interface (adio port) timing specifications table 6. avdd = 3.3 v 5%, dvdd = clkvdd = drvdd = 3.3 v 10%, unless otherwise noted parameter temp test level min typ max unit read operation (see figure 50) output data rate full ii 5 80 msps three-state output enable time (t pzl ) full ii 80 ns three-state output disable time (t plz ) full ii 3 ns rx data valid time (t dv ) full ii 3 ns rx data output delay (t od ) full ii 4 ns write operation (see figure 49) input data rate (1 interpolation) full ii 20 80 msps input data rate (2 interpolation) full ii 10 80 msps input data rate (4 interpolation) full ii 5 50 msps tx data setup time (t ds ) full ii 12.5 ns tx data hold time (t dh ) full ii 0 ns latch enable time (t en ) full ii 3 ns latch disable time (t dis ) full ii 3 ns
ad9866 rev. 0 | page 8 of 48 full-duplex data interface (tx and rx port) timing specifications table 7. avdd = 3.3 v 5%, dvdd = clkvdd = drvdd = 3.3 v 10%, unless otherwise noted parameter temp test level min typ max unit tx path interface (see figure 53) input nibble rate (2 interpolation) full ii 20 160 msps input nibble rate (4 interpolation) full ii 10 100 msps tx data setup time (t ds ) full ii 3 ns tx data hold time (t dh ) full ii 1 ns rx path interface (see figure 54) output nibble rate full ii 10 160 msps rx data valid time (t dv ) full ii 3 ns rx data hold time (t dh ) full ii 0 ns explanation of test levels i: 100% production tested. ii: 100% production tested at 25c and guaranteed by design and characterization at specified temperatures. iii: sample tested only. iv: parameter is guaranteed by design and characterization testing. v: parameter is a typical value only. vi: 100% production tested at 25c and gu aranteed by design and characterization for industrial temperature range.
ad9866 rev. 0 | page 9 of 4 8 absolute maximum ra tings table 8. p a r a me t e r r a t i n g elec tri c a l a v dd , clk v dd v o ltage 3.9 v max dvdd , dr vdd v o ltage 3.9 v max r x +, rx?, reft , refb ?0.3 v t o a v d d + 0.3 v ioutp+, ioutp? ?1.5 v to a v d d + 0.3 v ioutn+, ioutn?, iout g+, iout g? ?0.3 v t o 7 v oscin, x t a l ?0.3 v t o cl vdd + 0.3 vs refio , ref a dj ?0.3 v t o a v d d + 0.3 v dig i tal i n put and o utput v o ltag e ?0.3 v t o dr vd d + 0.3 v dig i tal o utput c u rr en t 5 ma max environ m en t a l o p era t ing t e mp er a tur e r a nge ( a mbien t ) ?40c to +85c m a ximum junc tion t e mpera tur e 125c l e ad t e mper a tur e (s older i ng , 10 s) 150c stor age t e mpera tur e r a nge ( a mbien t ) ?65c to +150c s t r e s s es a b o v e t h os e lis t e d u n de r t h e a b s o l u t e m a xim u m r a tin g s m a y ca use pe rm a n en t d a ma g e t o t h e devi ce . t h is i s a st re ss r a t i n g on l y ; f u nc t i on a l op e r a t i o n of t h e d e v i c e a t t h e s e or a n y o t h e r con d i t io n s ab o v e t h o s e i n dica t e d in t h e op era t io nal s e c t io n o f t h is sp e c if ic a t io n is no t im plie d . e x p o sur e t o a b s o l u te max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . thermal c h ar a c teristics ther mal resis t a n c e : 64-le ad l f cs p (4-l a y er b o a r d). ja = 24c/w ( p addle s o lder ed t o g r o u n d p l ane , 0 lpm a i r). ja = 30.8c/w (p addle no t s o ld er e d to g r o u nd plan e, 0 lpm a i r). esd c a ution esd (elec t r o sta t i c dischar g e) sensitiv e devic e . ele c tr os ta tic char g e s as high as 4000 v r e adily ac cumula te on the human body and t e st eq uipmen t and can dischar g e wi thout det e c t ion. although this pr odu c t f e a tur es pr o p r i etar y esd pr otec tio n cir c u i tr y , per m anen t damage ma y oc cur on devic e s subjec ted to high ener gy elec tr o s ta tic dischar g es . ther ef o r e , p r ope r esd pr ecaution s ar e r e c o mmended to a v oid per f or m a nc e degrada t ion or l o ss of func tiona l it y .
ad9866 rev. 0 | page 10 of 48 pin conf igura t ion and fu nction descriptions 04560-0-002 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 32 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 33 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 49 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 adio11/tx[5] adio10/tx[4] adio9/tx[3] adio8/tx[2] adio7/tx[1] adio6/tx[0] adio5/rx[5] adio4/rx[4] adio3/rx[3] adio2/rx[2] adio1/rx[1] adio0/rx[0] rxclk t xclk/txquiet txen/txsync rxen/rxsync drv dd d r vss clkout1 sd io sd o sc lk sen gain/pga[ 5 ] pga [ 4] pga [ 3] pga [ 2] pga [ 1] re fb a vss r eset pga [ 0] avss avss iout_n? iout_g ? avss avdd refio refadj avdd avss rx+ rx? reft avss avdd avss drv dd d r vss p w r_ dwn clkout2 dv dd d vss clkv dd oscin xta l clkv s s config mo de iout_g+ iout_n+ iout_p ? iout_p+ ad9866 top view (not to scale) pin 1 identifier f i gure 2. pin config ur ation ta ble 9. pi n f u nct i on des c ri pt i o ns p i n no . m n emonic mode 1 p i n f u nc tion 1 adio11 hd msb of adio bu ff er t x [5] fd msb of t x n i bbl e i n put 2C5 adio10C7 hd bits 10C7 of adi o buff er t x [4C1] fd bits 4C1 of t x n i bble i n put 6 adio6 hd bit 6 of adio bu ff er t x [0] fd lsb of t x n i bble i n put 7 adio5 hd bit 5 of adio bu ff er rx [5] fd msb of rx n i bbl e o utput 8, 9 adio4C3 hd bits 4C3 of adio buff er rx [4C3] fd bits 4C3 of rx n i bble o utput 10 adio2 hd bit 2 of adio bu ff er rx [2] fd bit 2 of rx n i bble o utput 11 adio1 hd bit 1 of adio bu ff er rx [1] fd bit 1 of rx n i bble o utput 12 adio0 hd lsb of adio buf f er rx [0] fd lsb of rx n i bble o utput 13 r x en hd adio buff er c o ntr o l i n put r x sy nc fd rx da ta s y nchr oniza t ion o utput 14 t x en hd t x p a th enable i n put t x sy nc fd t x da ta synchr o n iza t io n i n put 15 t x clk hd adio sample clock i n put tx q u i e t f d f a st t x d a c/ia mp p o w e r - d o w n
ad9866 rev. 0 | page 11 of 48 pin no. mnemonic mode 1 pin function 16 rxclk hd adio request clock input fd rx and tx clock output at 2 f adc 17, 64 drvdd digital output driver supply input 18, 63 drvss digital output driver supply return 19 clkout1 f dac /n clock output (l = 1, 2, 4, or 8) 20 sdio serial port data input/output 21 sdo serial port data output 22 sclk serial port clock input 23 sen serial port enable input 24 gain fd tx data port (tx[5:0]) mode select pga[5] hd or fd msb of pga input data port 25C29 pga[4C0] hd or fd bits 4C0 of pga input data port 30 reset reset input (active low) 31, 34, 36, 39 44, 47, 48 avss analog ground 32, 33 refb, reft adc reference decoupling nodes 35, 40, 43 avdd analog power supply input 37, 38 rx?, rx+ receive path ? and + analog inputs 41 refadj txdac full-scale current adjust 42 refio txdac reference input/output 45 iout_g? ?tx amp current output_sink 46 iout_n? ?tx mirror current output_sink 49 iout_g+ +tx amp current output_sink 50 iout_n+ +tx mirror current output_sink 51 iout_p? ?txdac current output_source 52 iout_p+ +txdac current output_source 53 mode digital interface mode select input low = hd, high = fd 54 config power-up spi register default setting input 55 clkvss clock osc./synthesizer supply return 56 xtal crystal osc. inverter output 57 oscin crystal osc. inverter input 58 clkvdd clock osc./synthesizer supply 59 dvss digital supply return 60 dvdd digital supply input 61 clkout2 f oscin /l clock output, (l = 1, 2, or 4) 62 pwr_dwn power-down input 1 hd = half-duplex mode; fd = full-duplex mode.
ad9866 rev. 0 | page 12 of 48 typical perf orm ance cha r acte ristics rx p a th ty pic a l performance char a c teristics av d d = cl kv dd = dv dd = dr vd d = 3.3 v , f os c i n = f ad c = 50 msps, lo w-pass filters f ?3 db = 2 2 mh z, ain = ?1 dbfs , rin = 50 ?, ha lf- or full-du ple x i n t e rfa c e, de f a ult power bi a s s e t t i ngs 04560-0-003 frequency (mhz) r e fer r e d to in pu t spec tr u m ( d b m ) 0 6.25 12.50 18.75 25.00 10 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 0 fund = ? 1dbfs sinad = 61.9dbfs enob = 10bits snr = 64.5dbfs thd = ? 65.4dbfs sfdr = ? 64.9dbc (third harmonic) rbw = 12.21khz f i g u re 3. spe c t r al p l ot w i t h 4k fft of i n put sinus o id wit h r x pga = 0 db and p in = 9 db m 04493-0-041 frequency (mhz) inp u t re fe rre d s p e ctrum (dbm) 0 5 10 15 20 25 ?30 ? 130 ? 120 ? 110 ? 100 ?90 ?80 ?70 ?60 ?50 ?40 rbw = 12.2khz figure 4. spect ra l p l ot w i th 4k fft of 8 4 -ca rri er dmt s i gn al wit h pa r = 10. 2 db , p in = ?33.7 dbm, and rxpga = 36 db 04560-0-005 input amplitude (dbfs) (0dbfs = 2v p-p) s i nad (dbfs ) thd (dbfs ) ?21 ? 18 ?15 ? 12 ?9 ?6 ?3 0 66 45 ?5 0 ?9 2 ?8 6 ?8 0 ?7 4 ?6 8 ?6 2 ?5 6 63 60 57 54 51 48 sinad @ 3.14v sinad @ 3.3v sinad @ 3.46v thd @ 3.14v thd @ 3.3v thd @ 3.46v figure 5. sinad an d thd vs. input amplitude and supply (f in = 8 mh z, lp f f ?3 d b = 26 m h z; rx pg a = 0 db) 04560-0-006 rxpga gain (db) s i nad (dbfs ) enob ( b it s) ?6 0 6 12 18 24 30 36 42 48 65 41 10.5 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 62 59 56 53 50 47 44 1mhz 5mhz 10mhz 15mhz 20mhz f i g u re 6. sina d / e n ob v s . r x pga ga in and fr eque ncy 04560-0-007 rxpga gain (db) thd (dbc ) ?6 0 6 12 18 24 30 36 42 48 ?55 ?85 ?80 ?75 ?70 ?65 ?60 1mhz 5mhz 10mhz 15mhz 20mhz f i g u re 7. t h d v s . r x pga ga in and f r eq uency 04560-0-008 rxpga gain (db) s i nad (dbfs ) thd (dbc ) ? 6 0 6 12 18 24 30 36 42 48 65 44 ?45 ?80 ?75 ?70 ?65 ?60 ?55 ?50 47 50 53 56 59 62 sinad @ +25 c sinad @ +85 c sinad @ ? 40 c thd @ +25 c thd @ +85 c thd @ ? 40 c f i gure 8. sinad / t h d performan ce vs. rxpga gain and t e mp er at ure ( f in = 5 mh z )
ad9866 rev. 0 | page 13 of 48 rx path ty pica l performa nce characteris t ic s : av d d = cl kv dd = dv dd = dr vd d = 3.3 v , f os c i n = f ad c = 80 msps, lo w-pass filters f ?3 db = 3 0 mh z, ain = ?1 dbfs , rin = 50 ?, ha lf- or full-du ple x i n t e rfa c e, de f a ult power bi a s s e t t i ngs 04560-0-009 frequency (mhz) r e fer r e d to in pu t spec tr u m ( d b m ) 0 1 02 0 3 04 10 ? 100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 fund = ? 1dbfs sinad = 62.4dbfs enob = 10.1bits snr = 63.4dbfs thd = ? 69.3dbfs sfdr = ? 70.5dbc (third harmonic) rbw = 19.53khz f i g u re 9. spe c t r al p l ot w i t h 4k fft of i n put sinus o id wit h r x pga = 0 db and p in = 9 db m 04560-0-010 frequency (mhz) in pu t r e fer r e d spec tr u m ( d b m ) 0 1 02 0 3 04 ?3 0 ? 130 ? 120 ? 110 ? 100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 rbw = 19.53khz 0 f i g u re 10. spect ra l pl ot wit h 4 k fft of 11 1-ca rr ier dm t si g n al wit h pa r = 11 d b , p in = ?3 3.7 db m, l p f ' s f ?3 d b = 3 2 m h z an d rxpga = 36 db 04560-0-011 input amplitude (dbfs) (0dbfs = 2v p-p) s i nad (dbfs ) thd (dbfs ) ?21 ? 18 ?15 ? 12 ?9 ?6 ?3 0 66 45 ?5 0 ?9 2 ?8 6 ?8 0 ?7 4 ?6 8 ?6 2 ?5 6 63 60 57 54 51 48 sinad @ 3.14v sinad @ 3.3v sinad @ 3.46v thd @ 3.14v thd @ 3.3v thd @ 3.46v f i gure 11. sinad and thd vs. input a m plitude and s u pp ly (f in = 8 mh z, lp f f ?3 d b = 26 m h z; r x pga = 0 db) 04560-0-012 rxpga gain (db) s i nad (dbfs ) enob ( b it s) ?6 0 6 12 18 24 30 36 42 48 65 62 41 44 47 50 53 56 59 10.5 10.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 5mhz 10mhz 15mhz 20mhz 30mhz f i gure 12. sinad/e n ob vs. rxpga gain and frequ e ncy 04560-0-013 rxpga gain (db) thd (dbc ) ?6 0 6 12 18 24 30 36 42 48 ?55 ?60 ?65 ?70 ?75 ?80 ?85 5mhz 10mhz 15mhz 20mhz 30mhz f i g u re 13. th d v s . r x pga gai n a n d fr equen c y 04560-0-014 rxpga gain (db) s i nad (dbfs ) thd (dbc ) ?6 0 6 12 18 24 30 36 42 48 65 61 59 56 53 50 47 44 41 ?40 ?80 ?75 ?70 ?65 ?60 ?55 ?50 ?45 sinad @ +25 c sinad @ +85 c sinad @ ? 40 c thd @ +25 c thd @ +85 c thd @ ? 40 c f i g u re 14. sina d/ t h d pe rf or m a nc e v s . r x pga ga in and t e mp er at ure ( f in = 1 0 m h z)
ad9866 rev. 0 | page 14 of 48 rx path ty pica l performa nce characteris t ic s : av d d = cl kv dd = dv dd = dr vd d = 3.3 v , f os c i n = f ad c = 80 msps, lo w-pass filters f ?3 db = 3 0 mh z, ain = ?1 dbfs , rin = 50 ?, ha lf- or full-du ple x i n t e rfa c e, de f a ult power bi a s s e t t i ngs 04560-0-015 input frequency (mhz) s nr (dbfs ) thd (dbc ) 0 5 10 15 20 35 30 65.0 60.5 61.0 61.5 62.0 62.5 63.0 63.5 64.0 64.5 60.0 ?5 2 ?5 4 ?5 6 ?5 8 ?6 0 ?6 2 ?6 4 ?6 6 ?6 8 ?7 0 ?7 2 snr @ 3.14v snr @ 3.3v snr @ 3.47v thd @ 3.14v thd @ 3.3v thd @ 3.47v f i gure 15. snr and thd vs. input f r eq uency and supp ly ( lpf f ?3 d b = 2 6 mh z; rxpga = 0 d b ) 04560-0-016 rxpga gain (db) inte grate d nois e ( v rms) n o ise spec tr a l d e n s ity ( n v/ h z ) 18 24 30 36 42 48 ?40 c +85 c +25 c 109.4 10.9 21.9 32.8 43.8 54.7 56.6 76.6 87.5 98.5 0 20 18 16 14 12 10 8 6 4 2 0 f i gure 16. input r e f e rr ed integr ated n o ise and no ise sp e c tra l d e nsity vs. rxp g a ga i n (lpf f ?3 d b = 2 6 m h z) 04560-0-017 gain (db) d c offset ( % of f u ll- scale) ? 6 0 6 12 18 24 30 36 42 48 5 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 device 1 device 2 device 3 device 4 f i gur e 1 7 . rx dc of fse t vs. rxp g a ga i n 04560-0-018 input frequency (mhz) s nr (dbfs ) thd (dbc ) 20 30 40 50 60 70 80 63 53 ?20 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 54 55 56 57 58 59 60 61 62 snr vs. msps @ 3.0v sup snr vs. msps @ 346v sup snr @ 3.13v thd @ 3.13v thd @ 3.46v thd @ 3.3v f i gure 18. snr and thd vs. s a mple rate and supply (lpf dis a bled; rxpga = 0 db; f in = 8 m h z) 04560-0-019 cutoff frequency (mhz) s nr (db) 0 1 02 03 04 05 06 07 08 0 45 38 39 40 41 42 43 44 f i g u re 19. snr v s . f ilt e r cut o f f fr eque n c y (50 m s ps; f in = 5 m h z; ain = ? 1 db; rxpga = 48 db) 04560-0-020 rxpga gain (db) gain step error (db) ?6 0 6 12 18 24 30 36 42 48 0.5 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 ad9865: gain step error @ +25 c ad9865: gain step error @ +85 c ad9865: gain step error @ ? 40 c f i gure 20. r x pga g a in step e r ro r v s . g a in (f in = 10 mh z)
ad9866 rev. 0 | page 15 of 48 rx path ty pica l performa nce characteris t ic s : av d d = cl kv dd = dv dd = dr vd d = 3.3 v , f os c i n = f ad c = 50 msps, lo w-pass filter di sabled, rxpga = 0 db, ain = ?1 dbfs, rin = 50 ?, ha lf- or full-du ple x i n t e rfa c e, de f a ult power bi a s s e t t i ngs 04560-0-021 time (ns) code 0 8 0 160 240 320 400 480 560 640 720 2048 256 512 768 1024 1280 1536 1792 f i g u re 21. r x pga s e t t ling t i me ?1 2 d b t o +4 8 db tr ans i t i on f o r dc input (f ad c = 50 msps, lp f disab l ed) 04560-0-022 input frequency (mhz) a m plitu d e r espon se ( d b ) 0 5 10 15 20 25 30 35 40 45 50 0 ?18 ?15 ?12 ?9 ?6 ?3 3.3v 3.0v 3.6v f i gur e 2 2 . rx lo w- p a ss fil t er am p l i t ude respo n se vs. suppl y (f ad c = 50 msps , f ?3 d b = 3 3 m h z, rxp g a = 0 db) 04560-0-023 frequency (mhz) atten @rxpg a = 0d b (db) 0 5 10 15 20 25 30 35 140 60 70 80 90 100 110 120 130 txdac isolation @ 0db iamp isolation @ 0db f i g u re 23. r x t o tx full-dup l ex is ol at i o n @ 0 r x pga s e t t i ng (note: atten @ r x pg a = x db = atten @ r x pga = 0 db ? r x pga g a i n ) 04560-0-024 time (ns) code 0 8 0 160 240 320 400 480 560 640 720 1152 1280 1408 256 384 512 640 768 896 1024 f i gure 24. rxpga s e ttling t i me f o r 0 d b to +5 d b tr ansit i on fo r dc input (f ad c = 50 msps, lp f disab l ed) 04560-0-025 input frequency (mhz) fundame n tal (db) 0 5 10 15 20 25 30 35 40 50 45 0 ?20 ?16 ?18 ?14 ?12 ?10 ?8 ?6 ?2 ?4 ?6db gain 0db gain +6db gain +18db gain +30db gain +42db gain f i gur e 2 5 . rx lo w- p a ss fil t er am p l i t ude respo n se vs. rxp g a gai n (lpf's f ? 3 db = 33 m h z) 04493-0-026 frequency (mhz) re s i s t ance ( ? ) cap acitance (pf) 5 105 95 85 75 65 55 45 35 25 15 420 320 10 0 1 2 3 4 5 6 7 8 9 330 340 350 360 370 380 390 400 410 r in c in f i gure 26. rx input imped a nc e vs. fr eq uency
ad9866 rev. 0 | page 16 of 48 txd a c p a th ty pic a l pe rformanc e char a c teristics av d d = cl kv dd = dv dd = dr vd d = 3.3 v , f os c i n = 50 msps and 80 msps, r set = 1 . 96 k?, 2:1 transformer couple d output (see figure 63) into 50 ? l o ad half-or full- du p l ex i n terface, d e fault power b i as settin g s 04493-0-072 frequency (mhz) dbm 0 5 10 15 20 25 10 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 f i g u re 27. d u al- t o n e spe c t r a l plot of t x da c's o u t p ut (f da t a = 5 0 m s ps, 4 int e rpol at i o n, 10 dbm p e ak p o wer , f 1 = 1 7 m h z, f2 = 1 8 m h z) 04560-0-028 2-tone center frequency (mhz) imd (dbfs ) ( r el at ive t o peak po wer) 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 ?6 5 ?9 0 ?8 5 ?8 0 ?7 5 ?7 0 10dbm 7dbm 4dbm f i gure 28. 2- t o ne i m d f r equenc y s w e e p vs. p e ak p o wer with f da t a = 50 msps, 4 inte r p o l a t io n 04560-0-029 2-tone center frequency (mhz) sfdr (dbfs) ( r el at ive t o peak po wer) 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 ?6 5 ?9 0 ?8 5 ?8 0 ?7 5 ?7 0 10dbm 7dbm 4dbm f i gure 29. 2- t o ne w o rs t spur f r equ e nc y s w eep v s . p e ak p o w e r with f da t a = 50 msps, 4 inte r p o l a t io n 04560-0-030 frequency (mhz) dbm 0 5 10 15 20 25 30 35 40 10 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 f i g u re 30. d u al- t o n e spe c t r a l plot of t x da c's o u t p ut (f da t a = 8 0 m s ps, 2 int e rpol at i o n, 10 dbm p e ak p o wer , f 1 = 2 7 .1 m h z, f2 = 2 8 . 7 m h z) 04560-0-031 2-tone center frequency (mhz) imd (dbfs) ( r el at ive t o peak po wer) 0 5 10 15 20 25 30 ?6 5 ?9 0 ?8 5 ?8 0 ?7 5 ?7 0 10dbm 7dbm 4dbm f i gure 31. 2- t o ne i m d f r equenc y s w e e p vs. p e ak p o wer with f da t a = 80 msps, 2 inte r p o l a t io n 04560-0-032 2-tone center frequency (mhz) sfdr (dbfs) ( r el at ive t o peak po wer) 0 5 10 15 20 25 30 ?6 5 ?9 0 ?8 5 ?8 0 ?7 5 ?7 0 10dbm 7dbm 4dbm f i gure 32. 2- t o ne w o rs t spur f r equ e nc y s w eep v s . p e ak p o w e r with f da t a = 80 msps, 2 inte r p o l a t io n
ad9866 rev. 0 | page 17 of 48 txdac path ty pical perfor mance characteristic s: av d d = cl kv dd = dv dd = dr vd d = 3.3 v , f os c i n = 50 msps and 80 msps, r set = 1. 96 k?, 2:1 transformer couple d output (see figure 63) in to 50 ? load , half- or full-d u p l ex i n terface, d e fault power b i as settin g s 04560-0-033 frequency (mhz) dbm 0 5 10 15 20 25 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ? 100 par = 11.4 rms = ? 1.4 dbm f i g u re 33. spec t r a l p l ot of 8 4 - c ar ri er o f dm t e s t v e c t o r f da t a = 5 0 m s ps, 4 interpol at i o n) 04493-0-079 frequency (mhz) dbm 0 2 5 5 0 7 5 100 125 150 175 200 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ? 100 par = 11.4 rms = ? 1.4dbm f i g u re 34. wideb a n d spec t r al pl ot of 8 8 -subc a r r ie r ofdm t e s t v e c t or (f da t a = 5 0 m s ps, 4 int e rpol at i o n) 04560-0-035 aout (dbfs) snr and 2 - tone imd (dbfs) ( r el at ive t o peak po wer) ?2 4 ? 2 1 ?1 8 ? 1 5 ? 1 2 ? 9 ? 6 ? 3 0 105 100 55 60 65 70 75 80 85 90 95 snr 2-tone imd f i gure 35. snr and sfdr vs. p ou t (f ou t = 1 2 .5 5 m h z, f da t a = 5 0 m s ps, 4 i n terpol at i o n) 04493-0-081 frequency (mhz) dbm 0 5 10 15 20 25 30 35 40 ?20 ? 100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 par = 11.4 rms = ? 1.4dbm f i g u re 36. spec t r a l p l ot of 1 11- ca rr ie r ofdm t e s t v e c t o r (f da t a = 8 0 m s ps, 2 int e rpol at i o n) 04493-0-082 frequency (mhz) dbm 0 2 0 4 0 6 0 8 0 100 120 140 160 ?20 ? 100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 par = 11.4 rms = ? 1.4dbm f i g u re 37. wideb a n d spec t r al pl ot of 1 11- ca rri er ofdm t e s t v e c t o r (f da t a = 8 0 m s ps, 2 int e rpol at i o n) 04560-0-038 aout (dbfs) snr and 2 - tone imd (dbfs) ( r el at ive t o peak po wer) ?2 4 ? 2 1 ?1 8 ? 1 5 ? 1 2 ? 9 ? 6 ? 3 0 100 95 55 60 65 70 75 80 85 90 snr 2-tone imd f i gure 38. snr and sfdr vs. p ou t (f ou t = 2 0 mh z, f da t a = 80 m s ps, 2 int e rpo l at i o n)
ad9866 rev. 0 | page 18 of 48 iamp p a th ty pic a l pe rformanc e char a c teristics av d d = cl kv dd = dv dd = dr vd d = 3.3 v , f os c i n = 50 msps, r set = 1 . 58 k?, 1:1 transformer couple d output (see f i gure 64 a nd f i gure 65) i n t o 50 ? l o a d , ha lf- or full-du plex i n t e rfa c e, defa ult p o wer bi a s s e t t i ngs 04493-0-084 frequency (mhz) dbm 0 5 10 15 20 25 20 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 15 rbw = 2.3khz f i g u re 39. d u al- t o n e spe c t r a l plot of i a m p n o u t p ut (ia m p s e t t i ng s of i = 12 .5 ma, n = 4, g = 0, 2:1 t r ans f o r me r i n to 7 5 ? l o ad er , v c m = 4. 8 v ) 04493-0-085 frequency (mhz) dbm 0 5 10 15 20 25 0 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 par = 11.4 rms = 10.3dbm f i g u re 40. spec t r a l p l ot of 8 4 - c ar ri er o f dm t e s t v e c t o r u s ing ia m p n in c u rrent mod e conf igur ation (ia m p s e t t i ng s of i = 1 0 ma, n = 4, g = 0; v c m = 4. 8 v ) 04493-0-086 frequency (mhz) dbm 0 5 10 15 20 25 0 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 par = 11.4 rms = 10.4dbm f i g u re 41. spec t r a l p l ot of 8 4 - c ar ri er o f dm t e s t v e c t o r u s ing ia m p in v o lt ag e mode configu r at ion with a v dd = 5 v (pbr 9 51 t r ans i s t or s, ia m p s e t t i ng s of i = 6 ma, n = 2, g = 6) 04493-0-087 vcm (v) oip3 (dbm) 3.0 3.5 4.0 4.5 5.0 48 5mhz 10mhz 15mhz 20mhz 2.5mhz 30 46 44 42 40 38 36 34 32 f i g u re 42. iou t n t h ir d- o r d e r i n te r c ep t v s . com m on-m od e v o lt ag e (ia m p s e t t i ng s of i = 1 2 . 5 ma, n = 4, g = 0, 2:1 t r ans f o r m e r int o 7 5 ? l o ad) 04493-0-088 vcm (v) oip3 (dbm) 3.0 3.5 4.0 4.5 5.0 42 5mhz 10mhz 15mhz 20mhz 2.5mhz 30 40 38 36 34 32 f i g u re 43. iou t g t h ir d- o r d e r i n te r c ep t v s . com m on-m od e v o lt ag e (ia m p s e t t i ng s of i = 4. 2 5 ma, n = 0, g = 6, 2:1 t r ans f o r m e r int o 7 5 ? l o ad) 04493-0-089 frequency (mhz) dbm 0 5 10 15 20 25 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 par = 11.4 rms = 9.8dbm rbw = 10khz f i g u re 44. spec t r a l p l ot of 8 4 - c ar ri er o f dm t e s t v e c t o r u s ing ia m p in v o lt ag e mode configu r at ion with a v dd = 3.3 v (pbr 9 51 t r ans i s t or s, ia m p s e t t i ng s of i = 6 ma, n = 2, g = 6)
ad9866 rev. 0 | page 19 of 48 serial port table 10. spi register mapping power-up default value mode = 0 (half-duplex) mode = 1 (full-duplex) address (hex) 1 bit break- down description width config = 0 config = 1 config = 0 config = 1 comments spi port configuration and software reset 0x00 (7) 4-wire spi 1 0 0 0 0 (6) lsb first 1 0 0 0 0 (5) s/w reset 1 0 0 0 0 default spi configuration is 3-wire, msb first. power control registers (via pwr_dwn pin) 0x01 (7) clock syn. 1 0 0 0 0 (6) txdac/iamp 1 0 0 0 0 (5) tx digital 1 0 0 0 0 (4) ref 1 0 0 0 0 (3) adc cml 1 0 0 0 0 (2) adc 1 0 0 0 0 (1) pga bias 1 0 0 0 0 (0) rxpga 1 0 0 0 0 pwr_dwn = 0 default setting is for all blocks powered on. 0x02 (7) clk syn. 1 0 0 0 1* (6) txdac/iamp 1 1 1 1 1 (5) tx digital 1 1 1 1 1 (4) ref 1 1 1 1 1 (3) adc cml 1 1 1 1 1 (2) adc 1 1 1 1 1 (1) pga bias 1 1 1 1 1 (0) rxpga 1 1 1 1 1 pwr_dwn = 1 default setting* is for all functional blocks powered down except pll. *mode = config = 1 setting has pll powered down with oscin input routed to rxclk output. half-duplex power control 0x03 (7:3) tx off delay 5 (2) rx _txen 1 (1) tx pwrdn 1 (0) rx pwrdn 1 0xff 0xff n/a n/a default setting is for txen input to control power on/off of tx/rx path. tx driver delayed by 31 1/f data clock cycles. pll clock multiplier/synthesizer control 0x04 (5) duty cycle enable 1 0 0 0 0 (4) f adc from pll 1 0 0 0 0 (3:2) pll divide-n 2 00 00 00 00 (1:0) pll multiplier-m 2 01 10* 01 01 default setting is duty cycle restore disabled, adc clk from oscin input, and pll multiplier 2 setting. *pll multiplier 4 setting. 0x05 (2) oscin to rxclk 1 0 0 0 1* (1) invert rxclk 1 0 0 0 0 (0) disabled rxclk 1 0 0 0 0 full-duplex rxclk normally at nibble rate. *exception on power-up. 0x06 (7:6) clkout2 divide 2 10 10 10 10 (5) clkout2 invert 1 0 0 0 0 (4) clkout2 disable 1 0 0 0 1* (3:2) clkout1 divide 2 10 10 10 10 (1) clkout1 invert 1 0 0 0 0 (0) clkout1 disable 1 0 0 0 1* default setting is clkout2 and clkout1 enabled with divide-by-2. *clkout1 and clkout2 disabled.
ad9866 rev. 0 | page 20 of 48 power-up default value mode = 0 (half-duplex) mode = 1 (full-duplex) address (hex) 1 bit break- down description width config = 0 config = 1 config = 0 config = 1 comments rx path control 0x07 (5) initiate offset cal. 1 0 0 0 0 (4) rx low power 1 0 1* 0 1* (0) rx filter on 1 1 1 1 1 default setting has lpf on and rx path at nominal power bias setting. *rx path to low power. 0x08 (7:0) rx filter tuning cut-off frequency 8 0x80 0x61* 0x80 0x80 refer to low-pass filter section. tx/rx path gain control 0x09 (6) use spi rx gain 1 (5:0) rx gain code 6 0x00 0x00 0x00 0x00 default setting is for hardware rx gain code via pga or tx data port. 0x0a (6) use spi tx gain 1 (5:0) tx gain code 6 0x7f 0x7f 0x7f 0x7f default setting is for tx gain code via spi control. tx and rx pga control 0x0b (6) pga code for tx 1 0 0 0 0 (5) pga code for rx 1 1 1 1 1 (3) force gain strobe 1 0 0 0 0 (2) rx gain on tx port 1 0 0 1* 1* (1) 3-bit rxpga port 1 0 1** 0 0 default setting is rxpga control active. *tx port with gain strobe (ad9875/ad9876 compatible). ** 3-bit rxpga gain map (ad9975 compatible). tx digital filter and interface 0x0c (7:6) interpolation factor 2 01 00 01 01 (4) invert txen/txsync 1 0 0 0 0 (2) ls nibble first* 1 n/a n/a 0 0 (1) txclk neg. edge 1 0 0 0 0 (0) twos complement 1 0 0 1 1 default setting is 2 interpolation with lpf response. data format is straight binary for half- duplex and twos complement for full-duplex interface. *full-duplex only. rx interface and analog/digital loopback 0x0d (7) analog loopback 1 0 0 0 0 (6) digital loopback* 1 0 0 0 0 (5) rx port 3-state 1 n/a n/a 0 0 (4) invert rxen/rxsync 1 0 0 0 0 (2) ls nibble first* 1 n/a n/a 0 0 (1) rxclk neg. edge 1 0 0 0 0 (0) twos complement 1 0 0 1 1 data format is straight binary for half-duplex and twos complement for full- duplex interface. analog loopback: adc rx data fed back to txdac. digital loopback: tx input data to rx output port. *full-duplex only. digital output drive strength, txdac output, and rev id 0x0e (7) low drive strength 1 0 0 0 0 (0) txdac output 1 0 0 0 0 0x0f (3:0) rev id number 4 0x00 0x00 0x00 0x00 default setting is for high drive strength and iamp enabled. tx iamp gain and bias control 0x10 (7) select tx gain 1 (6:4) g1 3 (2:0) n 3 0x44 0x44 0x44 0x44 secondary path g1 = 0, 1, 2, 3, 4. primary path n = 0, 1, 2, 3, 4. 0x11 (6:4) g2 3 (2:0) g3 3 0x62 0x62 0x62 0x62 secondary path stages: g2 = 0 to 1.50 in 0.25 steps and g3 = 0 to 6.
ad9866 rev. 0 | page 21 of 48 power-up default value mode = 0 (half-duplex) mode = 1 (full-duplex) address (hex) 1 bit break- down description width config = 0 config = 1 config = 0 config = 1 comments 0x12 (6:4) stand_secondary 3 (2:0) stand_primary 3 0x01 0x01 0x01 0x01 standing current of primary and secondary path. (7:5) cpga bias adjust 3 (4:3) spga bias adjust 2 0x13 (2:0) adc bias adjust 4 0x00 0x00 0x00 0x00 current bias setting for rx paths functional blocks. refer to page 41. 1 bits that are undefined should always be assigned a 0. register map description the ad9866 contains a set of programmable registers described in table 10 that can be used to optimize its numerous features, interface options, and performance parameters from its default register settings. registers pertaining to similar functions have been grouped together and assigned adjacent addresses to minimize the update time when using the multibyte serial port interface (spi) read/write feature. bits that are undefined within a register should be assigned a 0 when writing to that register. the default register settings were intended to allow some applications to operate without the use of an spi. the ad9866 can be configured to support a half- or full-duplex digital interface via the mode pin with each interface having two possible default register settings determined by the setting of the config pin. for instance, applications that need to use only the tx or rx path functionality of the ad9866 can configure it for a half- duplex interface (mode = 0) and use the txen pin to select between the tx or rx signal path with the unused path remaining in a reduced power state. the config pin can be used to select the default interpolation ratio of the tx path and rxpga gain mapping. serial port interface (spi) the serial port of the ad9866 has 3- or 4-wire spi capability allowing read/write access to all registers that configure the devices internal parameters. registers pertaining to the spi are listed in table 11. the default 3-wire serial communication port consists of a clock (sclk), serial port enable ( sen ), and a bidirectional data (sdio) signal. sen is an active low control gating read and write cycles. when sen is high, sdo and sdio are three-stated. the inputs to sclk, sen , and sdio contain a schmitt trigger with a nominal hysteresis of 0.4 v centered about vddh/2. the sdo pin remains three-stated in a 3-wire spi interface. table 11. spi registers pertaining to spi options address (hex) bit description 0x00 (7) enable 4-wire spi (6) enable spi lsb first a 4-wire spi can be enabled by setting the 4-wire spi bit high , causing the output data to appear on the sdo pin instead of on the sdio pin. the sdio pin serves as an input only, throughout the read operation. note that the sdo pin is active only during the transmission of data and remains three-stated at any other time. an 8-bit instruction header must accompany each read and write operation. the instruction header is shown in table 12. the msb is a r/ w indicator bit with logic high indicating a read operation. the next two bits, n1 and n0, specify the number of bytes (one to four bytes) to be transferred during the data transfer cycle. the remaining five bits specify the address bits to be accessed during the data transfer portion. the data bits immediately follow the instruction header for both read and write operations. table 12. instruction header information msb lsb 17 16 15 14 13 12 11 10 r/w n1 n0 a4 a3 a2 a1 a0 the ad9866 serial port can support both most significant bit (msb) first or least significant bit (lsb) first data formats. figure 45 illustrates how the serial port words are built for the msb first and lsb first modes. the bit order is controlled by the spi lsb first bit (register 0, bit 6). the default value is 0, msb first. multibyte data transfers in msb format can be completed by writing an instruction byte that includes the register address of the last address to be accessed. the ad9866 automatically decrements the address for each successive byte required for the multibyte communication cycle.
ad9866 rev. 0 | page 22 of 48 sc l k s dat a sc l k s dat a r/ w n1 a1 a2 a3 a4 a0 n2 d7 1 d6 1 d1 n d0 n r/ w n1 a1 a2 a3 a4 a0 n 2 d0 1 d1 1 d7 n d6 n 04560-0-045 dat a t r ans f e r c y c l e i n s t ru ct i o n c y c l e dat a t rans f e r c y c l e i n s t ruct i o n c y c l e sen sen f i gure 45. spi ti ming , msb f i rst (up p er) and lsb f i rst (l ow er) w h en t h e spi l s b f i rst b i t is s e t hig h , t h e s e r i a l p o r t in t e r p r e ts b o t h in st r u c t io n an d d a t a b y t e s ls b f i rst. m u l t i b y t e d a t a tra n sfers in ls b fo r m a t ca n be c o m p let e d b y wr i t in g an in s t r u c t io n b y t e t h a t i n cl udes t h e r e g i s t er addr es s o f t h e f i rs t addr es s t o be ac ces s ed . th e ad9866 a u t o ma tic a l l y in cr em en ts t h e addr es s fo r e a ch s u cces s iv e b y t e r e q u ir e d for t h e m u l t i b yte co mm unic a t io n c y c l e . f i gur e 46 i l l u s t ra t e s t h e t i min g r e q u ir em e n ts for a wr i t e o p e r a t i o n t o th e s p i p o rt . a f t e r t h e s e ri a l p o rt e n a b l e ( se n ) sig n al g o es lo w , da ta (s di o) p e r t a i nin g t o t h e ins t r u c t io n h e ader is r e ad on the r i sin g edges o f th e c l o c k ( s clk). t o ini t i a t e a wr i t e op era t ion, t h e r e ad/ n o t - w r i t e b i t is s e t lo w . af t e r t h e i n s t r u c t io n h e ader is r e ad , t h e e i g h t da t a b i t s p e r t a i ni n g t o t h e sp e c if ie d r e g i s t er a r e s h if t e d in t o t h e s d i o p i n on t h e r i sin g e d g e o f t h e n e xt eig h t clo c k c y cles. i f a m u l t i b y t e co mm u n ic a - t i o n c y cle is sp e c if ie d , t h e dest i n a t ion addr ess i s de cr em e n te d (ms b f i rst) a nd a n o t h e r eig h t b i ts o f da t a a r e sh if te d in. t h is p r o c ess r e p e a t s i t s e lf un t i l a l l t h e b y t e s sp e c if ie d in t h e in st r u c - tio n h e ader (n1 , n0 b i ts) a r e s h if t e d in. se n m u s t r e ma in lo w d u r i n g the da t a tra n sf er o p era t io n, o n l y g o in g hig h a f t e r t h e last b i t is shif t e d in. d7 d6 a0 d1 sen n1 n0 t s sclk sdio 1/ f sclk t low t hi t ds t dh r/w d0 t h 04560- 0- 046 f i g u re 46. spi w r it e o p er at io n ti ming f i g u re 4 7 i l lu st r a te s t h e t i m i ng f o r a 3 - w i re re a d op e r a t i o n to th e s p i po r t . a f t e r se n g o es lo w , da t a (s d i o) p e r t a i nin g t o t h e in st r u c t io n h e a d er is r e ad o n t h e r i sin g e d ges o f sclk. a r e ad o p era t ion o c c u rs if t h e r e ad / n o t -wr i t e i n d i c a t o r is s e t hig h . af t e r t h e addr ess b i ts o f t h e i n s t r u c t io n h e ader a r e r e ad , t h e eig h t da t a b i ts p e r t a i nin g t o t h e s p e c if ie d r e g i s t e r a r e s h if t e d o u t of t h e sdio pi n on t h e f a l l i n g e d ge s of t h e ne x t e i g h t cl o c k c y cles. i f a m u l t i b y t e co m m unic a t io n c y cle is sp e c if ie d i n t h e in st r u c t io n h e a d er , a simi la r p r o c ess as p r e v i o u sly des c r i b e d for a m u l t i b yt e s p i wr i t e op era t io n a p plies. th e s d o p i n r e main s t h re e - st a t e d i n a 3 - w i re re a d o p e r a t i o n . d7 d6 a0 d1 sen n1 t s s clk sdio 1/ f sclk t low t hi t ds t dh r/w d0 t ez a2 a1 t dv 04560- 0- 047 f i g u re 47. spi 3-w i re r e ad o p er at i o n tim i ng f i g u re 4 8 i l lu st r a te s t h e t i m i ng f o r a 4 - w i re re a d op e r a t i o n to th e s p i po r t . th e ti m i n g i s si m i la r t o th e 3-wi r e r e a d o p e r a t i o n w i th th e e x c e p t i o n t h a t d a ta a p pe a r s a t th e s d o p i n , wh i l e th e s d i o p i n r e ma i n s hig h im p e dan c e t h r o ug h o u t t h e o p era t ion. t h e s d o p i n i s a n a c ti v e o u t p u t o n l y d u ri n g th e da ta tra n sf e r p h a s e a n d re m a i n s t h re e - st a t e d a t a l l ot he r t i me s . a0 sen n1 t s sclk sdio 1/ f sclk t low t hi t ds t dh r/w t ez a2 a1 t dv d7 d6 d1 sdo d0 t ez 04560- 0- 048 f i g u re 48. spi 4-w i re r e ad o p er at i o n tim i ng
ad9866 rev. 0 | page 23 of 48 digit a l i n terf ace the dig i tal in t e r f ace p o r t is co nf igura b le f o r half-d u p lex o r f u l l - dup l e x op e r a t i o n by pi n - s t r a ppi ng t h e m o de p i n l o w or h i g h , r e s p ecti v e l y . i n h a lf- d u p le x m o d e , th e d i gi tal in t e rfa c e po r t b e c o m e s a 1 0 - bi t bi d i re c t i o n a l b u s c a l l e d t h e a d io p o r t . in f u l l - d u plex m o de, t h e dig i t a l i n ter f ac e p o r t is divide d in to t w o 6-b i t po r t s called t x [5:0] a n d rx[5:0] f o r si m u l t a n eo us t x a n d rx o p er a t io ns. i n t h is m o de, da t a i s t r a n sfer r e d b e tw e e n t h e as ic a nd ad9866 in 6-b i t ni bb les. th e ad9866 als o f e a t ur es a f l exi b le dig i t a l in t e r f ace f o r u p da tin g t h e rxpg a an d txpga ga in r e g i sters v i a a 6- b i t pga p o r t o r tx[ 5 :0] po r t fo r fast u p da t e s, o r vi a t h e sp i p o r t fo r s l o w er u p da t e s. s e e t h e rx pga co n t r o l s e c t i o n . half-dupl e x mode the half-d u p lex m o de f u n c t i o n s as f o l l o w s wh e n the m o d e p i n is t i e d lo w . the b i dir e c t io n a l adi o p o r t is ty p i ca l l y sha r e d i n b u r s t fa s h i o n bet w een th e tra n sm i t p a th a n d r e ce i v e pa t h . t w o con t r o l sig n als, t x e n an d r x e n , f r o m a ds p (o r dig i tal asic ) c o n t ro l t h e bu s d i re c t i o n by e n abl i ng t h e a d io p o r t s in p u t l a tch an d o u t p ut dr i v er , r e sp e c t i vely . t w o clo c k sig n a l s, t x cl k and r x clk, a r e us e d to la tch t h e tx i n p u t d a t a an d c l oc k th e r x o u t p u t d a t a , r e s p ec ti v e l y . th e a d i o po r t ca n also be d i sa b l e d b y se t t in g t x en a n d r x en l o w (de f a u l t set t in g ) , th us al lo win g i t t o be connec t e d t o a s h a r e d b u s. i n t e r n al l y , the ad i o p o r t co n s ists o f a n in p u t la t c h f o r th e tx p a th in p a ral l e l wi t h an o u t p u t l a t c h wi th t h r e e-s t a t e o u t p u t s f o r th e rx p a t h . t x en is us ed t o ena b le the in p u t la t c h; r x e n is us e d t o t h r e e- s t a t e t h e o u t p u t l a t c h. a f i v e -s am ple-de ep fifo is us e d o n t h e tx a nd rx p a t h s t o a b s o rb an y phas e dif f er en ce betw een t h e ad9866 s in t e r n al clo c ks an d t h e ex t e r n al l y s u pp l i e d c l o c k s ( t x c l k , r x c l k ) . t h e a d io bu s a c c e pt s i n put da ta- w o r d s in t o th e tra n sm i t p a th w h en th e t x en p i n i s h i g h , t h e r x e n p i n i s lo w , a n d a clo c k is p r es en t o n t h e t x cl k p i n, a s s h ow n i n fi g u re 4 9 . tx c l k t xen a d i o [9 :0 ] r xen tx 0 tx 2 tx 3 t x 4 tx 1 t dis 04560-0-049 t dh t en t ds f i gure 4 9 . t r a n s m i t d a ta inp u t t i mi ng di a g r a m the tx i n t e r p ol a t io n f i l t er(s) fol l o w in g t h e ad io p o r t ca n b e f l us h e d wi th z e r o s, i f th e c l oc k si gn al i n t o th e t x c l k p i n i s p r es en t fo r 33 clo c k c y cles a f t e r t x e n g o es lo w . n o t e t h a t t h e d a t a on t h e adio b u s is ir r e le van t o v er t h is in te r v a l . the o u t p u t f r o m t h e r e cei v e p a t h is dr i v e n on t o t h e ad i o b u s w h en t h e r x en p i n is hig h , and a clo c k is p r es en t on t h e r x cl k p i n. w h i l e t h e o u tp u t l a tch is ena b le d b y r x e n , va lid da ta a p pea r s o n th e b u s a f t e r a 6- c l oc k - c y c l e d e la y d u e t o th e i n te r n a l f i f o d e l a y . n o te t h a t r x d a t a i s not l a tch e d b a c k i n to t h e tx p a t h , if t x e n is hig h d u r i n g t h is in t e r v a l w i t h t x cl k p r es en t. the a d i o bus b e comes t h r e e-s t a t e d o n ce t h e r x en pi n re tu r n s l o w . f i g u re 5 0 i l lu st r a te s t h e re c e ive p a t h output ti m i n g . t pzl 04560- 0- 050 rxe n a d i o [9 :0 ] rx c l k t vt t plz t od rx0 rx1 rx2 rx3 f i gure 50. rec e ive d a t a o u tput tim i n g d i ag r a m t o add f l exi b i l i t y t o t h e dig i t a l i n t e r f ace p o r t , s e v e ral p r og ra m- min g o p t i on s a r e a v a i la b l e in t h e s p i r e g i s t ers. th e s e o p t i on s ar e lis t e d in t a b l e 1 3 . th e defa u l t tx a n d rx da t a i n p u t fo r m a t s a r e st r a ig h t b i na r y , b u t ca n b e ch a n ge d to t w o s co m p le m e n t . t h e defa u l t t x en and r x en s e t t ings a r e ac t i ve hig h , b u t can b e s e t t o o p posi t e pola ri ti e s , th us allo w i n g th e m t o sha r e th e sa m e co n t r o l . i n this cas e , t h e ad i o p o r t ca n stil l b e p l ace d o n t o a s h a r e d b u s b y dis a b l in g i t s in p u t la t c h via t h e con t r o l sig n al , a n d dis a b l i n g t h e o u t p u t dr i v er v i a t h e sp i r e g i s t er . the clo c k t i ming ca n b e i n dep e nden t ly cha n ge d o n t h e t r a n sm i t a nd r e cei v e p a t h s b y s e le c t i n g ei t h er t h e r i sin g o r fal l in g cl o c k e d ge as t h e va lid a t i n g /s am plin g e d ge o f t h e clo c k. l a st ly , t h e o u t p u t dr i v er s st r e n g t h c a n b e r e d u ce d fo r lo w e r da t a r a te a p pl ica t ion s . table 13. spi r e gisters for half-du p lex i n terface a ddress (he x ) b i t d e s c r i p t i o n 0x0c ( 4 ) i n v e r t t x e n (1) t x clk nega tiv e edge ( 0 ) t w os complemen t 0x0d (5) rx por t thr e e - s t a t e (4) i n v e r t r x en (1) r x clk nega tiv e edge ( 0 ) t w os complemen t 0x0e (7) l o w dig i tal driv e s t r e ngth the half-d u p lex in t e r f ace ca n b e co nf igur e d t o ac t lik e a sla v e or a mast er t o t h e dig i t a l a s i c . a n exa m ple o f a sla v e conf igura - tio n is sh o w n in f i gur e 51. i n this exa m p l e , th e ad9866 accep t s al l th e c l o c k and co n t r o l sig n al s f r o m th e dig i t a l as i c . b e c a us e t h e s a m p li n g clo c ks fo r t h e d a c a nd ad c a r e der i ve d i n ter - n a ll y f r o m th e o s c i n si gn al , i t i s r e q u i r ed tha t th e t x cl k a n d r x c l k si gn als be a t e x a c tl y th e sa m e f r eq ue n c y a s th e o s c i n sig n al . the p h as e r e la tio n shi p s am o n g t h e t x c l k, r x c l k, and o s c i n si gn als ca n be a r b i tra r y . i f th e di gi tal a s i c ca nn o t p r o v ide a lo w j i t t e r clo c k s o ur ce t o oscin, co n s ider usin g t h e ad9866 t o g e n e ra t e t h e c l o c k f o r i t s d a c and ad c an d p a s s t h e desir e d clo c k sig n a l to t h e d i g i t a l asi c vi a clk o ut1 o r clk o ut2.
ad9866 rev. 0 | page 24 of 48 to tx digital filter 12 adio [11:0] oscin rxen ad9866 from rx adc 12 rxen txen txen txclk rxclk dac_clk adc_clk clkout digital asic 04560-0-051 tx/rx data[11:0] f i g u re 51. e x a m pl e of a h a lf -d up lex d i g i t a l int e r f ac e wit h a d 98 66 s e r v i n g as t h e sl ave f i gur e 52 s h o w s a half-d u p lex in t e r f ace wi t h t h e ad9866 ac t i ng as t h e mast er , gen e ra t i n g al l t h e r e q u ir e d clo c ks. clk o ut1 prov i d e s a cl o c k e q u a l to t h e b u s d a t a r a te t h a t i s fe d to t h e a s i c as we l l as bac k t o t h e t x clk and r x cl k in p u ts. this in t e r f ace has t h e ad van t a g e o f r e d u cin g t h e dig i t a l as ic s p i n c o u n t b y t h re e. th e asic ne e d s on ly to ge ne r a t e a b u s c o n t rol si gn al th a t co n t r o ls th e da ta f l o w o n t h e b i di r e cti o n a l b u s. to tx digital filter 12 adio [11:0] tx/ r x d a ta[1 1:0 ] clkout1 ad9866 from rx adc 12 rxen txen bus_ctr txclk rxclk clkin digital asic 04560-0-052 oscin from crystal or master clk f i g u re 52. e x a m pl e of a h a lf -d up lex d i g i t a l int e r f ac e wit h a d 98 66 s e r v i n g as t h e m a s t e r f u ll -duplex mode the f u l l -d u p lex m o de i n t e r f ace is s e le c t e d w h e n t h e mo d e p i n is t i e d hi g h . i t c a n b e us e d fo r f u l l - o r ha lf-d u p l e x a p plic a t io n s . the dig i t a l i n ter f ace p o r t is divi de d i n to tw o 6- b i t p o r t s ca l l e d t x [5:0] a n d rx[5:0], all o wi n g sim u l t a n eo us tx a nd rx o p er a - t i o n s f o r f u l l - d u p l e x ap p l i c at i o n s . in h a l f - d u p l e x ap p l i c at i o n s , th e tx[5:0] p o r t ca n als o be us e d t o p r o v ide a f a s t u p da te o f the rxpga (ad98 76 bac k wa r d co m p a t i b le) d u r i ng a n rx o p er a t ion. this fe a t ur e is enab le d b y defa u l t an d ca n b e us e d to r e d u ce t h e r e q u ir e d p i n co un t of t h e a s ic (r efer t o rxpga c o n t ro l s e c t i o n f o r more d e t a i l ) . i n ei t h er a p plic a t io n, tx and rx d a t a a r e t r an sfer r e d b e t w e e n th e a s i c and ad9866 in 6-b i t ( o r 5-b i t) nib b l es a t twice th e i n te r n a l i n put / out p ut word r a te s of t h e tx i n te r p ol a t i o n f i lte r a nd a d c. n o t e t h a t t h e txd a c u p da te ra te mu s t n o t be le s s t h a n t h e ni bb le ra t e . th er efo r e , t h e 2 o r 4 in ter p ola t io n f i l t er m u st b e us e d w i t h a f u l l - d u p lex in t e r f ace. the ad9866 ac ts as t h e mas t er , p r o v idin g r x clk as an o u t p u t c l oc k th a t i s use d f o r th e tim i n g o f bo th t h e t x [5: 0 ] a n d r x [5: 0 ] p o r t s. r x cl k a l wa y s r u n s a t t h e nib b l e r a te and can b e i n ver t e d o r dis a b l e d v i a an s p i r e g i ster . b e ca us e r x c l k is der i ve d f r o m th e c l ock syn t h e si z e r , i t r e m a i n s a c ti v e , p r o v i d e d th a t th i s f u nc t i on a l bl o c k re m a i n s p o we re d on . a bu f f e r e d ve r s i o n of t h e sig n al a p p e a r ing a t os cin ca n als o be dir e c t e d t o r x clk b y s e t t in g b i t 2 o f reg. 0x05. this f e a t ur e al lo ws th e ad9866 t o b e co m p letely p o w e r e d do w n (i n c ludin g t h e clo c k sy n t h e si zer ) w h i l e s e r v in g as t h e mas t er . the tx[5:0] p o r t o p era t e s in t h e fol l o w in g mann er wi t h t h e s p i r e g i s t er def a u l t s e t t in gs. t w o co n s e c u t i v e nibb les o f t h e tx da t a a r e m u l t i p lexe d to get h er to fo r m a 10- b i t da t a - w o r d in tw o s c o mp l e m e n t f o r m at . t h e c l o c k ap p e a r i n g o n t h e r x c l k p i n i s a b u f f er e d v e rsi o n o f t h e i n t e r n al clo c k us e d b y t h e tx[5:0] p o r t s in p u t l a t c h w i t h a f r e q ue n c y t h a t is a l wa y s twic e t h e a d c s a m p le ra t e (2 f ad c ). da ta f r om the tx[5:0] p o r t is r e ad o n the ri s i n g edg e o f this s a m p lin g c l o c k, as il l u s t ra t e d in t h e timin g di a g r a m sh own in f i gur e 53. t x2l s b tx 0 l s b t hd t ds rxclk txsync tx[5:0] 04560-0-053 tx 1 m s b tx 1 l s b tx 2 m s b t x3l s b tx 3 m s b f i gure 53. t x [5: 0 ] p o r t f u l l - d u p l ex t i mi ng d i agr a m th e t x sy nc s i g n a l i s u s e d to i n d i c a te to w h i c h word a ni bbl e b e lo n g s. the f i rs t nibb le o f e v er y w o r d is r e ad w h ile t x s y n c is lo w as t h e m o st sig n if ica n t n i bble . th e s e cond n i bb le o f t h a t s a me w o r d is r e ad o n t h e f o l l o w in g t x s y n c hig h leve l as t h e le ast sig n if ic a n t nib b l e . i f t x s y n c is lo w fo r mo r e t h a n on e c l oc k c y c l e , th e la s t tra n smi t da t a i s r e a d co n t in uo us l y un til t x s y n c is b r oug h t hig h fo r t h e s e con d nib b l e o f a ne w tra n smi t w o rd . this f e a t ur e can be us e d t o f l us h the in t e r p ola t o r f i l t ers wi th zer o s. n o t e tha t t h e gain sig n al m u s t be k e p t lo w du r i n g a t x o p e r a t i o n . the rx[5:0] p o r t o p era t e s in t h e fol l o w in g mann er wi t h t h e s p i r e g i s t er def a u l t s e t t in gs. t w o co n s e c u t i v e nibb les o f t h e rx da t a a r e m u l t i p lexe d to get h er to fo r m a 10- b i t da t a - w o r d in tw o s co m p lem e n t f o r m a t . the rx da t a is valid on t h e r i sin g edg e o f rx c l k , a s i l l u s t r a t e d i n t h e t i min g d i a g ra m sh o w n i n f i g u re 5 4 . the r x s y nc s i g n a l i s u s e d to i n di c a te to w h i c h w o r d a ni bb le b e lo n g s. th e f i rs t ni bb le o f e v er y w o r d is t r a n smi t t e d w h i l e r x s y n c is lo w as t h e m o st sig n if ica n t nib b l e. t h e s e cond nibb le o f t h a t s a m e w o r d is t r a n smi t te d o n t h e fol l o w in g r x s y n c hi g h le v e l as t h e le ast sig n if ican t n i bb l e .
ad9866 rev. 0 | page 25 of 48 04560-0-054 rxclk rxsync rx[5:0] rx0 l sb r x1m s b r x1l s b r x2m s b r x3l s b rx3 m sb t dv t dh f i g u re 54. f u ll-d u p l ex r x p o r t ti mi ng t o add f l exi b i l i t y t o t h e f u l l - d uplex dig i t a l i n t e r f ace p o r t , s e v e ral p r og ra mmin g o p t i on s a r e a v a i la b l e in t h e s p i r e g i s t ers. th e s e o p t i on s ar e lis t e d i n t a b l e 14. the t i mi ng fo r t h e tx[5:0] a nd/o r rx [ 5 :0] p o r t s ca n b e i n d e p e n d e n t l y cha n ge d b y s e le c t ing ei t h er t h e r i sin g o r fal l in g clo c k e d g e as t h e s a m p lin g /vali d a t i n g edg e o f the c l o c k. i n ver tin g r x clk ( v ia b i t 1 or reg. 0x0d) a f f e ct s bo th t h e r x a n d t x in t e r f a c e , be ca use th ey bo t h use rx c l k . table 14. spi registers for full-duplex inter f ace a ddress (he x ) b i t d e s c r i p t i o n 0x05 (2) oscin to rx clk (1) i n v e r t rx clk (0) dis a b l e r x clk 0x0b (2) rx gain on t x por t 0 x 0 c ( 4 ) i n v e r t t x sy nc (3) t x 5/ 5 nibbl e (2) ls nibble first (1) t x clk nega tiv e edge (0) t w os complemen t 0x0d (5) rx por t thr e e - s t a t e (4) i n v e r t r x sy nc (3) rx 5/ 5 nibbl e (2) ls nibble first (1) r x clk nega tiv e edge (0) t w os complemen t 0x0e (7) l o w driv e s t r e ngth the def a u l t tx a nd rx da t a i n pu t fo r m a t s a r e t w o s co m p le m e n t , b u t ca n b e ch a n ge d to st r a ig h t b i na r y . th e defa u l t t x s y n c and r x s y n c s e t t i n gs ca n b e chan ge d such t h a t t h e f i rst nib b l e o f t h e w o r d a p p e a r s w h i l e t x s y n c , r x s y n c , o r b o t h a r e h i g h . als o , th e le as t sig n if ica n t ni bb le ca n be s e le c t e d as the f i rs t nib b l e o f t h e w o r d (ls nib b l e f i rs t). the o u t p u t dr i v er s t r e n g t h ca n a l s o b e r e d u ce d fo r lo w e r da t a r a te a p plic a t i o n s . f i gur e 55 sh o w s a p o ssib le dig i t a l in t e r f ace b e t w e e n an a s ic a nd t h e ad986 6. th e ad9866 s e r v es as th e mas t er g e n e ra tin g t h e r e q u ir e d clo c ks fo r t h e a sic. this i n t e r f ac e r e q u ir es t h a t t h e a s ic r e s e r v e 16 p i n s fo r t h e i n ter f ace , as s u ming a 6- b i t nib b l e wid t h and t h e u s e o f t h e tx p o r t fo r rxpga ga i n co n t r o l . n o t e tha t t h e a s i c p i n al lo c a tio n can be r e d u ced b y 3, if a 5-b i t nib b l e wi d t h is us e d an d t h e gain (o r ga in st r o b e ) o f t h e rxpg a i s co n t r o ll ed via th e s p i po r t . 04560-0-055 to tx digital filter 10/12 ad9865/ad9866 from rx adc 10/12 rxsync txsync tx_sync rxclk clkout1 clkout2 clkin digital asic oscin from crystal or master clk gain optional tx data[5:0] r x d a ta [5 :0 ] r x [5 :0 ] rx_sync mux demux t x [5 :0 ] 6 to rx pga f i g u re 55. e x a m pl e of a f u l l -d up lex d i g i t a l inte r f ace wi th o p tio n al rxpg a g a i n co nt r o l via t x [ 5 :0 ] rxpga c o ntr o l the ad9866 con t a i n s a dig i tal pga in the rx p a th tha t is us e d to ex tend t h e d y na mic r a n g e. t h e rx p g a c a n b e p r o g r a m m e d o v er a ?12 db t o +48 db wi th 1 db r e s o l u tio n u s in g a 6-b i t w o r d , a nd wi t h a 0 db s e t t i n g c o r r esp o n d i n g to a 2 v p-p i n p u t s i g n a l . th e 6 - b i t word i s fe d i n to a l u t t h a t i s u s e d to di st r i bute t h e desir e d ga i n o v er t h r e e a m plif ica t ion s t a g es wi t h in t h e rx pa th . u p o n po w e r - u p , th e r x p g a g a i n r e gi s t e r is se t t o i t s mini m u m gain o f ?12 db . the rx pga ga i n ma p p i n g is sh own in f i gur e 56. t a b l e 15 lis t s t h e sp i r e g i s t ers p e r t a i nin g t o t h e rxpga.
ad9866 rev. 0 | page 26 of 48 04560-0-056 6-bit digital word-decimal equivalent gain ( d b) 0 48 24 60 66 ?1 2 ?6 0 6 12 18 24 30 36 42 54 42 48 30 36 61 2 18 f i g u re 56. d i g i t a l g a in m a p p ing of r x pg a table 15. spi registers rxpga control a ddress (he x ) b i t d e s c r i p t i o n 0x09 (6) enable rxpga upda t e via spi ( 5 : 0 ) rxpga gain c o de 0x0b (6) s e lec t t x pga vi a pga[5:0] (5) s e lec t rxpga via pga[5:0] (3) enable sof t w a r e gain str obe C full- d u plex (2) enabl e rx pga upda t e via t x [5:0] C full- d u plex (1) 3-bit rxpga gain mapping C half- d uplex the rx pga gai n r e g i ster c a n b e u p da te d v i a t h e tx [ 5 :0] p o r t , t h e pg a[5:0] p o r t , o r t h e s p i p o r t . th e f i rs t two m e t h o d s al lo w f a st u p d a te s of t h e r x p g a g a i n re g i ste r and s h ou l d b e co n s ider e d fo r dig i t a l a g c f u nc t i o n s r e q u ir in g a fast clos e d - lo o p r e s p o n s e . the s p i p o r t al lo ws dir e c t u p da t e an d r e ad back o f th e rxpga g a in r e g i st er via reg. 0x09 wi th a n u p da te ra t e limi ted t o 1.6 m s ps (wi t h sclk = 32 mh z). n o t e tha t b i t 6 o f reg. 0x09 m u s t be s e t f o r a r e ad o r wr i t e o p era t io n. u p d a ti n g th e r x p g a v i a th e t x [ 5 : 0 ] po rt i s a n o p t i o n o n l y i n full - d u p l e x m o d e . 1 i n this cas e , a hig h lev e l o n t h e g a in p i n 2 wi t h tx s y nc lo w p r og ra m s t h e pga s e t t i n g on ei t h er t h e r i sin g edg e o r fal l in g edg e o f r x clk, as sh own in f i gur e 57. the gai n p i n m u s t be h e l d hig h , txs y n c m u s t be he ld lo w , a nd gai n da t a m u st b e st ab le fo r o n e o r m o r e clo c k c y cles to u p d a te t h e rxp g a ga in s e t t ing. a lo w le v e l on t h e g a in p i n e n abl e s d a t a to b e fe d to t h e di g i t a l i n te r p ol a t i o n f i lte r . th i s in t e r f ace s h o u l d b e co n s i d er e d w h en u p g r ading exis t i n g desig n s f r o m th e ad98 76 mxfe p r o d uc t o r half-d u p lex a p p l ic a t io n s tr yin g t o minimize a n as i c s p i n co un t. 1 de fa ult set t i n g f o r ful l - d uple x m o de ( m od e = 1 ) . 2 th e g a in st robe ca n a lso be set i n so ft wa re vi a r e g. 0x0b, bi t 3 fo r continuous upd a ting. this el iminates the requirement f o r external gain s i gnal , red u cing the as ic pin co unt by 1. t su rx c l k tx syn c tx [ 5 : 0 ] t hd ga in ga in 04560-0-057 f i g u re 57. u p dat i n g r x pg a v i a t x [5: 0 ] i n f u ll -d uplex m o de u p d a ti n g th e r x p g a ( o r t x p g a ) v i a th e pga [ 5 : 0 ] po rt i s a n opt i on f o r b o t h t h e h a l f - d upl e x 3 a nd f u l l - d u p lex in ter f aces. t h e pga p o r t co n s is ts o f a n in p u t b u f f er tha t p a s s es th e 6-b i t da ta a p p e a r in g a t i t s in p u t dir e c t ly t o t h e rxpg a (o r txpga) ga i n r e gi s t e r wi th n o ga ti n g si gn al r e q u i r ed . b i t 5 o r b i t 6 o f r e g. 0x0b is us ed t o s e lec t w h et h e r t h e da ta u p da t e s th e rxpg a o r t x p g a g a i n re g i s t e r . in app l i c at i o n s t h at s w i t c h b e t w e e n rxpga and tx pga ga in co n t rol via pg a[5:0], be c a r e f u l tha t th e r x pga (o r t x pga ) i s n o t in a d v e r t e n tl y loa d ed wi th t h e w r o n g da ta d u ri n g a tra n si ti o n . i n t h e ca se o f a n r x pga t o t x pga tra n si tio n , f i r s t d e se lect th e r x pga ga in r e gi s t e r , u p da t e t h e pg a[ 5:0] p o r t wi t h t h e des i r e d tx pg a ga i n s e t t ing, an d t h e n s e le c t t h e txpga ga in r e g i s t er . t h e rxpga also o f f e r s a n al t e rn a t i v e 3- b i t w o r d ga i n m a p p i n g opt i on 4 tha t p r o v ides a ?12 db to +36 db s p a n in 8 db in cr e- m e n t s as sh o w n in t a b l e 16. the 3-b i t w o r d is dir e c t ed t o pga[5:3] wi t h pga[5] bein g th e m s b . this f e a t ur e is b a c k wa rd co m p a t i b le wi th th e ad9975 m xfe a n d al lo ws dir e c t in t e r f ac- in g t o t h e cx11 647 o r int5130 h o mep l ug 1.0 p h ys. table 16. pga timing for ad9975 backward com p atible mode digital ga in s e tting pga[5:3 ] decimal g a in (db) 0 0 0 0 ?12 0 0 1 1 ? 1 2 010 2 ? 4 011 3 4 100 4 1 2 1 0 1 5 2 0 1 1 0 6 2 8 1 1 1 7 3 6 3 de fa ult set t i n g f o r h a lf- duplex m o d e ( m od e = 0 ) . 4 de fa ult set t i n g f o r mod e = 0 a n d c o n fig =1.
ad9866 rev. 0 | page 27 of 48 txpga c o n t rol the ad9866 als o co n t a i ns a dig i tal pg a in t h e tx p a th dis t r i b - u t ed bet w een t h e t x d a c a n d i a mp . th e t x p g a i s used t o co n t r o l t h e p e a k c u r r en t f r o m t h e txd a c and i a mp o v er a 7.5 db an d 19.5 db s p an, r e s p ec t i v e l y , wi th 0.5 db r e s o l u tio n . a 6-b i t w o r d is us e d t o s e t t h e tx pga a t ten u a t ion acco r d i n g t o th e ma p p in g sho w n in f i gur e 5 8 . th e txd a c ga in ma p p i n g is a p p l icab le o n l y when b i t 0 o f reg. 0x0e is s e t, and o n l y the 4 ls bs o f th e 6 - b i t ga in w o rd a r e r e levan t . 04560-0-058 6-bit digital code (decimal equivalent) tx atte nuation (dbfs ) 0 8 16 24 32 40 48 56 64 0 ?20 ?16 ?18 ?14 ?12 ?10 ?8 ?6 ?2 ?4 ?1 ?17 ?19 ?15 ?13 ?11 ?9 ?7 ?3 ?5 txdacs ioutp output has 7.5db range iamps ioutn and ioutg outputs has 19.5db range f i g u re 58. d i g i t a l g a in m a p p ing of t x p g a the txpg a r e g i s t er can b e u p da t e d via t h e pg a[5:0] p o r t o r s p i p o r t . th e f i rs t m e t h o d s h o u l d b e co n s ider e d f o r fas t u p da t e s o f t h e txpg a r e g i s t er . i t s o p era t io n is simi la r to t h e des c r i p t ion in t h e rxpg a c o n t r o l s e c t io n. the s p i p o r t al lo ws dir e c t up d a t e a n d re a d b a ck of t h e t x p g a re g i ste r v i a r e g . 0 x 0 a w i t h a n u p da te ra t e l i mi t e d t o 1.6 ms ps (sclk = 32 mh z). b i t 6 o f reg 0x0a m u s t be s e t f o r a r e ad o r wr i t e o p era t io n. t a b l e 17 lis t s t h e s p i r e g i s t ers p e r t a i nin g t o t h e txpga. the txpg a co n t r o l r e g i ster defa u l t s e t t in g i s fo r minim u m a tten u a t io n (0 db fs) wi th t h e pg a[5:0] p o r t dis a b l ed f o r tx ga in co n t r o l . table 17. spi r e gisters txpga control a ddress (he x ) b i t d e s c r i p t i o n 0x0a (6) enable t x pga upda t e via spi ( 5 : 0 ) t x pga gain c o de 0x0b (6) s e lec t t x pga vi a pga[5:0] ( 5 ) s e lec t rxpga via pga[5:0] 0x0e (0) t x d a c outpu t (i a m p dis a bl ed)
ad9866 rev. 0 | page 28 of 48 transmit pa th the ad9866 (o r ad9865) tra n smi t p a t h co n s ists o f a s e lec t ab le dig i t a l 2/4 in t e r p ola t ion f i l t er , a 12-b i t (o r 10-b i t) tx d a c, a nd a c u r r en t-ou t p ut a m pl if ier (i amp), as sh ow n in f i gur e 59. n o t e tha t t h e add i ti o n al t w o b i ts o f r e so l u ti o n o f f e r e d b y th e ad9866 (vs. th e ad9865) r e s u l t in a 10 db t o 12 db r e d u c t ion in t h e p a ss -b and n o is e f l o o r . th e dig i t a l in t e r p ola t ion f i l t er rel a x e s t h e t x a n a l o g f i lte r i n g re qu i r e m e n t s by s i m u lt a n e o u sly r e d u ci n g t h e i m a g e s f r o m th e d a c r e co n s tr ucti o n p r oce s s wh ile in cr ea sin g th e a n alog f i l t e r s tra n si ti o n b a n d . th e d i gi tal in te r p ol a t ion f i lte r c a n a l s o b e by p a ss e d , re su l t i n g in l o we r dig i t a l c u r r en t co n s um pt io n. 10 a d 9 865/ad 9866 0 to ?7.5db 04560-0-059 0 to ?12db 2-4x iou t _ g + iou t _ n + iou t _ n ? iou t _ g ? iamp iout _p+ iout _p ? tx c l k t xen / syn c a d i o [ 1 1 :6 ]/ t x [5 :0 ] a d i o [1 1 : 6 ] / r x [5 :0 ] txdac f i g u re 59. f u nc t i o n al bl ock d i ag r a m o f t x p a t h digit a l in t e rpol a t i o n fil t ers the in p u t da ta f r o m th e tx p o r t ca n be f e d in t o a s e lec t ab le 2/4 in t e r p ol a t io n f i l t er o r dire c t ly in t o t h e t x d a c (fo r a ha lf- d u plex o n l y ). th e i n t e r p ol a t ion fac t o r fo r t h e di g i t a l f i l t er is s e t via s p i reg. 0x0 c wi th t h e s e t t in gs s h own in t a b l e 18. th e max i m u m in p u t w o r d ra te, f da t a , in t o t h e i n t e r p ola t ion f i l t er is 80 ms ps; th e maxim u m d a c u p da te ra te is 200 ms ps. th er e- f o r e , ap p l i c at i o n s w i t h i n p u t w o r d r a t e s at o r b e l o w 5 0 m s p s ca n b e n e f i t f r o m 4 in t e r p ola t io n, w h i l e a p pli c a t ion s wi t h in pu t w o r d r a tes b e twe e n 50 ms ps and 80 ms ps c a n b e n e f i t f r o m 2 in t e r p ol a t ion. table 18. i n ter p olation factor set via spi re g. 0x0c bits [7:6] in t e rpola t ion f a c t or 00 4 01 2 10 1 (hal f- dupl ex onl y ) 11 do not use the i n ter p ol a t i o n f i l t er co n s ist s o f tw o cas c ade d ha lf-b and f i l t e r s t a g es w i t h e a ch s t a g e p r o v i d ing 2 in t e r p ol a t ion. th e f i rs t st a g e f i l t er co n s is ts o f 43 t a ps. th e s e co nd s t a g e f i l t er , o p era t in g a t t h e hig h er da t a ra te , co n s ists o f 11 t a ps. th e n o r m a l ize d wi de b a nd a nd p a ss -b and f i l t er r e sp o n s e s ( r ela t i v e f da t a ) f o r th e 2 an d 4 lo w-p a ss in ter p ola t io n f i lters a r e sh own in f i gur e 60 a nd f i gur e 61, r e s p ecti v e l y . n o t e th a t th e s e r e s p o n ses also i n c l ud e th e inh e r e n t sin c (x) fr o m th e txd a c r e co n s tr ucti o n p r oce s s a nd can be us e d t o es tima t e an y p o s t a n alog f i l t er in g re qu i r e m e n t s . the p i p e line del a ys o f th e 2 and 4 f i l t er r e s p on s e s a r e 21.5 and 2 4 cl o c k c y cl es , resp e c t i vel y , rel a t i ve to f da t a . the f i l t er de l a y is a l s o t a k e n in to co n s idera t ion fo r a p plica t ion s co nf igur e d fo r a half-d u p lex in t e r f ace wi t h t h e half-d u plex p o w e r - do w n m o de ena b le d . this fe a t ur e al lo ws t h e us er t o s e t a p r og ra mma b l e del a y t h a t p o w e rs do wn t h e tx d a c and i a mp o n ly a f ter t h e las t tx in p u t s a m p le has p r o p aga t e d thr o ug h t h e dig i tal f i l t er . s e e t h e p o w e r c o n t r o l s e c t io n fo r m o r e det a i l s . 04560-0-060 normalized frequency (relative to f data ) wide band response (db) 0 10 1.25 2.00 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 0 1.75 0.75 1.00 1.50 wide band 0.50 0.25 pass band response (db) 2.5 ? 2.5 ? 2.0 ? 1.5 ? 1.0 ? 0.5 0 0.5 1.0 1.5 2.0 pass band ?1.0db @ 0.441 f data f i g u re 60. f r equen c y r e s p ons e of 2 i n terpol at i o n f i lte r (nor ma li zed to f da t a ) 04560-0-061 normalized frequency (relative to f data ) wide band response (db) 0 10 2.5 4.0 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 0 3.5 1.5 2.0 3.0 wide band 1.0 0.5 pass band response (db) 2.5 ? 2.5 ? 2.0 ? 1.5 ? 1.0 ? 0.5 0 0.5 1.0 1.5 2.0 pass band ?1.0db @ 0.45 f data f i g u re 61. f r equen c y r e s p ons e of 4 i n terpol at i o n f i lte r (nor ma li zed to f da t a ) txd a c a n d iamp arc h i t ec ture the tx p a t h con t a i n s a tx d a c a l o n g w i t h a c u r r en t a m plif ier , i a mp . th e t x d a c r e co n s tr uct s th e o u t p u t o f th e in t e r p o l a t i o n f i l t er a nd s o ur c e s a dif f er en t i al c u r r en t o u t p u t t h a t c a n e i t h er b e dir e c t e d t o an ext e r n al lo ad o r f e d in t o the i a m p f o r f u r t h e r a m plif ic a t ion. t h e txd a c s and i a mps s p e a k c u r r en t o u t p u t s a r e dig i tal l y p r og ra mma b l e o v er a 0 t o ?7.5 db a nd 0 t o ?19.5 db ra n g e , r e s p e c ti v e l y , in 0.5 db in cr em en ts. n o t e tha t this as s u m e s def a u l t r e g i s t er s e t t in g s f o r reg. 0x10 a nd reg. 0x11.
ad9866 rev. 0 | page 29 of 48 a p plica t ion s de ma nding t h e hi g h est sp e c t r a l p e r f o r ma n c e a nd/o r lo w e st p o w e r co n s um p t i o n can us e t h e tx d a c o u t p ut dir e c t ly . the tx d a c is c a p a ble o f deli ver i n g a p e a k sig n a l po w e r - u p t o 10 d b m wh ile m a in ta in i n g r e spect a b l e lin e a r i t y p e r f o r ma n c e , as s h o w n in f i gure 27 thr o ug h f i gur e 38. f o r p o w e r - s e n s i t i v e a p plic a t io ns r e q u ir in g t h e hig h est tx p o w e r ef f i cien c y , th e txd a c s f u l l -s cal e c u r r en t o u t p u t can b e r e d u ce d t o as lo w as 2 m a an d i t s lo ad resist o r s size d t o p r o v ide a sui t ab le vol t a g e swi n g t h a t can b e am plif ie d b y a lo w p o w e r o p - a m p-b a s e d dr i ver . m o st a p plic a t ion s r e q u ir in g hig h er p e a k sig n a l p o w e rs (u p t o 23 dbm) sh o u ld co n s ider usin g t h e i a mp . th e i a mp can b e co nf igur e d as a c u r r en t s o ur ce fo r lo ads ha ving a w e l l def i n e d im p e dan c e (50 ? o r 75 ? sys t em s) o r a v o l t a g e s o ur ce (wi t h t h e a d d i t i on of a p a i r of n p n t r ans i s t or s ) f o r p o or ly d e f i ne d l o a d s ha vin g v a r y in g i m p e dance (such as p o w e r li n e s ) . f i gur e 62 s h o w s th e e q ui v a len t s c h e ma ti c o f th e t x d a c a n d i a mp . th e txd a c p r o v ides a dif f er en t i al c u r r en t o u t p u t a p p e a r in g a t i o u t p+ an d iou t p?. i t can b e m o d e le d as a dif f er en t i al c u r r en t s o ur ce ge n e ra t i n g a sig n al- d ep e n de n t ac cu rr e n t , wh en ?i s has a p e ak c u r r en t o f i alo n g wi t h tw o dc cu rr e n t so u r c e s , so u r c i n g a standin g c u r r en t eq ual t o i. th e f u l l - s c ale o u t p u t c u r r en t, i o u t fs, is e q ual t o t h e s u m o f t h es e s t an din g c u r r en t s o ur ces (i o u tfs = 2*i). 04560- 0- 062 n (i+ ? i) n (i ? ? i) g (i+ ? i) g (i ? ? i) i o utn? i o utn+ iou t g ? iou t g+ ? i s i i txdac refadj refio ioutp+ ioutp? i + ? i i? ? i i off1 r set 0.1 f i off1 i off2 xg xg xn xn i off2 iamp f i g u re 62. equiv a le nt s c h e m a t i c of t x da c and ia m p the val u e o f i is det e r m in e d b y th e r set val u e a t t h e ref a d j p i n a l o n g w i t h t h e tx p a t h s dig i t a l a t te n u a t ion s e t t i n g. w i t h 0 db a t t e n u a t ion, th e val u e o f i is ) / 23 . 1 ( 16 set r i ? = eq uat i on 1. f o r e x am pl e, an r set val u e o f 1.96 k? r e s u l t s in i eq ual t o 10.0 ma wi t h i o utfs e q ual to 20.0 ma. n o te tha t t h e refi o p i n p r o v ide s a no mina l b a nd ga p r e fer e n c e vol t a g e o f 1.23 v a nd sh o u ld b e d e co u p le d to a n a l o g g r o u n d v i a a 0.1 f ca p a c i t o r . the dif f er en t i al c u r r en t o u t p u t o f t h e tx d a c i s al wa ys co n- n e ct ed t o th e i o u t p p i n s , b u t ca n be d i r e ct e d t o th e i a mp b y s e t t in g b i t 0 o f reg 0x0e. a s a res u l t , the i o utp p i n s mu s t r e ma in com p lete ly o p en, if t h e i a mp is t o b e us e d . t h e i a mp co n t a i n s tw o se ts o f curr e n t m i rr o r s th a t a r e used t o r e p l i c a t e t h e txd a c s c u r r en t o u t p ut w i t h a s e le c t a b le gain. th e f i rs t s e t o f c u rr en t mir r o r s is desig n a t e d as t h e p r ima r y p a t h , p r o v iding a g a i n f a c t or of n t h at i s pro g r a m m a bl e f r om 0 to 4 i n st e p s of 1 via b i ts 2:0 o f reg. 0x10 wi th a defa u l t s e t t in g of n = 4. b i t 7 o f th i s r e gi s t e r mu s t b e s e t t o o v er wr i t e t h e def a u l t s e t t in gs o f t h is r e g i s t er . this dif f er en t i al p a t h ex hib i ts t h e b e s t li n e a r i t y p e r f o r m a n c e (s e e f i gur e 42) a nd is a v a i lab l e a t t h e io u t n+ a nd iout n? pin s . t h e max i m u m p e a k c u r r en t p e r o u tp u t is 100 ma and o c c u rs wh en the txd a c s s t anding c u r r en t, i, is s e t f o r 12.5 ma (i o u tfs = 25 ma) . the s e cond s e t o f c u rr en t mir r o r s is desig n a t e d as t h e s e con - d a r y p a t h prov i d i n g a g a i n f a c t or of g t h a t i s pro g r a m m a bl e f r o m 0 t o 36 via b i ts 6:4 o f reg. 0x10 a n d bi ts 6: 0 o f reg. 0x11 wi t h a defa u l t s e t t in g o f g = 12. this dif f er en t i a l p a t h is in te nde d to b e us e d in t h e vol t a g e m o d e co nf i g ur a t io n to b i as t h e ext e r n al np n tra n sis t o r s, be ca us e i t exhib i ts deg r ade d l i ne ar it y p e r f or m a n c e ( s e e fi g u re 4 3 ) rel a t i v e t o t h e pr i m ar y p a th . i t is c a p a ble o f sinkin g u p t o 180 ma o f p e ak c u r r en t in t o ei t h er i t s io utg+ o r i o u t g? p i n s . th e s e conda r y p a t h ac t u al l y co n s ists o f 3 ga in s t a g es (g1, g2, a n d g 3 ), whic h a r e indivi d u al l y p r og ra mma b l e as sh o w n i n t a b l e 1 9 . w h ile man y p e r m u t a t io n s ma y exis t t o p r o v i d e a f i xe d ga i n o f g, t h e lin e a r i t y p e r f o r ma nce o f a s e conda r y p a t h r e m a in s r e l a t i vely i n d e pen d e n t o f th e v a ri o u s in di v i d u al ga in set t in gs th a t a r e p o ssi b le t o achi e v e a p a r t ic u l a r o v era l l ga in fac t o r . b o t h s e t s of m i r r or s s i n k c u r r en t, b e ca us e t h e y o r ig ina t e f r o m nmos de vi ces. ther efo r e , e a ch o u t p ut p i n r e q u ir es a dc c u r r en t pa th t o a posi ti v e s u p p l y . al t h o u gh th e v o l t a g e o u t p u t o f ea c h o u t p ut p i n can s w i n g b e twe e n 0. 5 a nd 7 v , o p t i m u m ac pe rf o r m a n c e i s t y p i call y a c h i ev ed b y l i m i ti n g t h e a c v o l t a g e swi n g wi t h a dc b i as vol t a g e s e t b e tw e e n 4 t o 5 v . l a st ly , b o t h t h e s t an din g c u r r en t, i, a nd the ac c u r r en t, ?i s , f r o m t h e t x d a c a r e a m plif ie d b y t h e ga in fac t o r (n a nd g) wi t h t h e to t a l st an di n g c u r r en t dr a w n f r o m t h e p o si t i ve su p p ly b e in g e q ua l to i g n ? + ? ) ( 2 p r og ra mma b l e c u r r en t s o ur ces i o ff1 and i o ff2 via reg. 0x12 can b e us e d to i m p r o v e t h e p r ima r y a nd s e conda r y p a t h mir r o r s l i ne ar it y p e r f or m a n c e u n d e r c e r t ai n c o nd i t i o ns b y i n c r e a s i ng t h eir sig n al -t o-st a nding c u r r en t ra t i o . this fe a t u r e p r o v ides a ma rg inal im p r ov em e n t i n di s t or t i o n p e r f o r ma n c e u n der la rg e sig n al co ndi t i ons w h en t h e p e ak ac c u r r en t o f t h e r e co n s t r uc t e d w a v e f o rm f r eq ue n t l y a p p r oa ch es th e d c s t a n di n g curr e n t w i thin t h e tx d a c (0 to ?1 dbf s sine wa ve) c a usin g t h e i n ter n a l m i r r or s to tu r n of f . h o we ve r , t h e i m prove m e n t i n d i stor t i on p e r f o r ma n c e diminish es as t h e cr es t fac t o r (p e a k-t o -r m s r a t i o) o f t h e ac sig n a l in cr e a s e s. m o st a p plic a t ion s can dis a b l e t h es e
ad9866 rev. 0 | page 30 of 48 c u r r en t s o ur ces (s et t o 0 ma via reg. 0x12) t o r e d u ce t h e ia m p s c u r r e n t c o n s u m p t i o n . table 19. spi registers for txdac and iamp a ddress (he x ) bit description 0 x 0 e ( 0 ) t x d a c o u t p u t 0x10 ( 7 ) enable cur r e n t mir r o r gain setti ngs ( 6 : 4 ) sec o ndar y pa th first stage gain of 0 to 4 with ? = 1 (3) not us ed ( 2 : 0 ) p r imar y pa th nmos gain of 0 t o 4 with ? = 1 0x11 (7) d o n t car e ( 6 : 4 ) sec o ndar y pa th sec o nd stage gain of 0 to 1.5 with ? = 0.25 (3) not us ed ( 2 : 0 ) sec o ndar y pa th thir d stage gain of 0 to 5 with ? = 1 0x12 (6:4) ioff2, sec o ndar y pa th standing cur r en t (2:0) ioff1, pr imar y pa th standing c u r r en t t x progr a mmable gain c o ntrol t x pga fun c ti o n ali t y i s also a v a i la b l e t o set t h e peak o u t p u t c u r r en t f r o m t h e txd a c o r i a mp . the txd a c a nd i a m p a r e dig i t a l l y p r og ra mma b l e via t h e pga[5:0] p o r t o r s p i o v er a 0 db to ?7.5 db a nd 0 db to ?19.5 db r a n g e, r e sp e c t i vely , i n 0.5 db in cr em en ts. the tx pg a can b e co n s ider e d as two c a s c a d e d a t te n u a t o r s wi t h th e txd a c p r o v idin g 7.5 db ran g e in 0.5 db incr em en ts, an d th e i a mp p r o v idin g 12 db ra n g e in 6 db in cr em en ts. a s a r e s u l t , th e i a mp s com p osi t e 19.5 db sp a n is valid only if reg. 0x10 r e ma in s a t i t s d e fa u l t s e t t i n g o f 0x44. m o dif y in g t h is r e g i st er se t t in g co rr u p t s th e l u t a n d r e s u l t s in a n i n v a li d ga in m a p p i n g . tx da c o u t p u t o p e r a t i o n the dif f er en t i al c u r r en t o u t p u t o f t h e tx d a c c a n b e dir e c t e d to th e i o utp+ and i o utp? p i n s b y s e t t in g bi t 0 o f reg. 0x0e. an y lo ad co n n e c te d to t h es e p i n s m u st b e g r o u nd r e fer e n c e d to p r o v ide a dc p a t h fo r t h e c u r r en t s o ur ces. f i gur e 63 s h o w s t h e output s of t h e t x d a c d r iv i n g a d o ubly te r m i n ate d 1 : 1 t r a n s - fo r m er wi t h i t s cen t er -t a p t i e d to g r o u n d . th e p e ak-t o - p e a k vol t age, v p - p , acr o ss r l ( a n d io u t + to io u t ? ) i s e q u a l to 2*i*(r l //r s ). w i th i = 10 ma and r l = r s = 50 ?, v p-p is eq ua l t o 0.5 v wi th 1 db m o f p e a k p o w e r b e i n g del i ver e d to r l and 1 dbm b e i n g dissi p a te d i n r s . 04560-0-063 ioutn? ioutn+ ioutg? ioutg+ iou t _ p + iou t _ p ? 0 to ?7.5db 0 to ?12db iamp re fio re fadj r set 0.1 f r s 1:1 r l txdac f i g u re 63. t x da c o u t p ut d i rec t ly v i a center - t ap t r a n s f or me r t h e t x d a c i s ca pa b l e o f d e l i v e ri n g u p t o 1 0 db m peak po w e r t o a lo ad , r l . t o i n c r ease th e peak po w e r f o r a f i x e d s t a n di n g c u r r en t, o n e m u s t i n cr e a s e v p - p acr o s s i o u t p + a nd ? i ou t p ? by i n c r e a s i ng on e or more of t h e f o l l ow i n g p a r a me - te rs : r s , r l (i f pos s i b le ), a n d / o r th e t u rn s ra ti o , n , o f tra n sf o r m e r . f o r exa m ple , t h e r e m o val o f r s a nd t h e us e o f a 2:1 im p e dan c e ra ti o tra n sf o r m e r i n th e p r e v i o us e x a m p l e r e s u l t s i n 10 d b m o f peak po w e r ca p a b i li t i e s t o th e loa d . n o t e tha t in cr ea si n g th e p o we r output c a p a bi l i t i e s of t h e t x d a c re d u c e s t h e d i stor t i on p e r f o r ma n c e d u e t o t h e hig h er vol t a g e s w i n gs s e en a t i o u t p+ an d iou t p ? . s e e f i g u re 2 7 t h rou g h f i g u re 3 8 f o r p e r f o r m a nc e pl ot s on t h e t x d a c s a c p e r f or m a n c e. o p t i m u m d i s t or t i on p e r f o r ma n c e can typ i cal l y be achiev e d b y : ? li m i tin g th e peak pos i ti v e v io u t p + a nd v io u t p ? t o 0.8 v t o a v oi d o n s e t of t x d a c s output c o m p re ss i o n . ( t x d a c s v o l t a g e com p lian ce is a r o u nd 1. 2 v . ) ? limi tin g v p-p s e en a t i o utp + a nd i o utp? t o les s tha n 1.6 v . a p plica t ion s de ma nding hig h er o u t p u t volt a g e swi n gs an d p o w e r dr i v e ca p a b i li t i es can b e nef i t f r o m usin g t h e i a mp . iamp curre nt m o de o p er a t ion the i a mp ca n b e co nf igur e d fo r t h e c u r r en t m o de o p er a t io n as sho w n i n f i g u re 6 4 f o r lo a d s re m a i n i n g rel a t i v e ly c o nst a n t . i n th i s m o d e , th e p r i m a r y pa th m i rr o r s s h o u ld be used t o de li v e r t h e sig n al -dep e n de n t c u r r en t to t h e lo ad vi a a cen t er -t a p p e d t r ans f or me r , b e c a u s e it prov i d e s t h e b e s t l i ne ar it y p e r f or m a nc e . b e ca us e t h e mir r o r s exhi b i t a hi g h o u t p u t i m p e dan c e , t h e y can be e a sil y ba c k -t e r m i n a t e d (i f r e q u i r ed ). f o r peak si gn al curr en t s (i o u t pk u p t o 50 ma), o n l y th e pr i m ar y p a t h m i r r or g a i n shou l d b e u s e d f o r opt i m u m dis t o r t i o n p e r f o r ma n c e and p o w e r ef f i cien c y . the p r ima r y pa th s ga in sh o u ld be se t t o 4, w i th th e seco n d a r y pa th s ga i n s t a g es s e t t o 0 (reg. 0x10 = 0x84). th e txd a c s s t an din g c u r r en t, i, ca n b e s e t betw een 2. 5 ma and 12.5 ma wi t h t h e iou t p output s l e f t op e n . t h e iou t n output s shou l d b e c o n n e ct ed t o th e t r a n s f o r m e r , w i th th e i o u t g ( a n d i o u t p )
ad9866 rev. 0 | page 31 of 48 output s l e f t op e n f o r opt i m u m l i ne ar it y p e r f or m a n c e. t h e tra n sf o r m e r 1 shou l d b e sp e c if ie d to hand l e t h e d c st andi ng cu rr e n t , i bi a s , d r a w n b y t h e i a m p . a l s o , b e c a u s e i bi a s re m a i n s sig n a l indep e nd en t, a s e r i es r e si sto r (n o t sh o w n ) ca n b e i n s e r t e d be tw e e n a v dd a nd t h e tra n sfor m e r s cen t er -ta p t o r e d u ce the i a m p s c o m m on- m o d e vol t ag e, v cm , a n d r e d u c e t h e p o w e r dissi p a t io n on t h e ic. t h e v cm , b i as sh o u ld n o t exceed 5.0 v and t h e p o w e r di s s i p a t e d in t h e i a mp alo n e is as fol l o w s: cm iamp v i g n p ? ? + ? = ) ( 2 eq uat i on 2. txdac 04560-0-064 ioutn ? ioutn+ ioutg ? ioutg+ iou t _p+ iou t _p ? 0 to ?7.5db 0 to ? 12db iamp refi o refadj r set 0.1 f r l avdd 0.1 f i bias = 2 (n+g) 1 iout pk t:1 iout pk = (n+g) 1 p_out pk = (iout pk ) 2 t 2 r l f i gure 64. cur r ent mode o p er atio n a ste p - d ow n t r ans f or me r 1 wi th a t u r n ra t i o , t , c a n be us ed t o in cr e a s e t h e o u tp u t p o w e r , p_ou t , deliver e d to t h e lo ad . t h is ca us es t h e o u t p u t lo ad , r l , to b e re f l e c te d b a c k to t h e i a m p s dif f er en tial ou t p u t b y t 2 r e s u l t ing in a la rg er dif f er en t i a l v o l t a g e swi n g s e e n a t t h e i a mp s o u t p ut. f o r exa m ple , t h e i a mp can de li v e r 24 dbm o f p e ak p o w e r to a 50 ? lo ad , if a 1.41:1 s t ep - do wn tran sfo r m e r is us e d . this r e s u l t s in 5 v p-p v o l t a g e s w in gs a p pe a r i n g a t i o ut n + a n d i o ut n ? p i n s . f i gur e 42 s h o w s h o w th e th i r d o r d e r in t e r c e p t po in t , o i p3, o f th e i a mp v a ri e s a s a f u n c tion o f co mm on-m o d e v o l t a g e o v er a 2.5 mh z t o 20.0 mh z s p a n wi t h a 2 - t o n e sig n al ha vin g a p e a k p o w e r o f a p p r o x ima t e l y 24 db m wi t h i o ut pk = 50 ma. f o r a p plica t ion s r e q u ir in g a n iou t pk exce e d in g 50 ma, s e t t h e seco n d a r y s pa th t o d e li v e r th e a d d i ti o n al curr e n t t o t h e loa d . i o ut g+ and i o utn+ sh o u ld be sh o r t e d as we l l as i o ut g? an d i o u t n ? . if iou t pk r e p r es en ts t h e p e ak c u r r en t t o b e de li v e r e d t o t h e lo ad , t h en t h e c u r r en t ga in i n t h e s e conda r y pa th , g, ca n b e se t b y th e f o llo w in g eq ua ti o n : 4 5 . 12 / ? = pk iout g eq uat i on 3. the li n e a r i t y p e r f o r ma n c e b e com e s li mi te d b y t h e s e conda r y m i r r or p a t h s d i stor t i on . 1 t h e b6080 and bx6090 tr ansf or mers fr om p u lse eng i neer i n g ar e w o r t h y of c o ns id era t ion f o r c u r r en t and v o l t age mod e s. iamp vol t a g e mode oper a t ion the v o l t a g e m o de co nf igura t ion is sh o w n in f i gur e 65. this co nf igura t io n is sui t e d fo r a p pli c a t ion s ha vi n g a p o o r ly def i n e d lo ad t h a t c a n var y o v er a co n s ider a b le r a n g e. a l o w im p e dance v o l t a g e dr i v er c a n b e r e ali z e d w i t h t h e addi t i o n o f tw o ext e r n al rf b i p o la r n p n tra n sis t o r s (p hil l i p s p b r951) and r e sis t o r s. i n t h is co nf igura t i o n, t h e c u r r en t mir r o r s in t h e pr ima r y p a t h (i o u tn o u t p u t s) fe e d in t o s c alin g r e sis t o r s, r , g e n e r a tin g a dif f er en t i al v o l t a g e i n t o t h e b a s e s o f t h e n p n t r a n sis t o r s. th es e tra n sis t o r s a r e c o nf igur e d as s o ur ce fol l o w ers wi t h t h e s e co n- da r y p a t h c u r r en t mir r o r s a p p e a r in g a t ioutg + a nd i o u t g? p r o v idin g a sig n a l -dep e nden t b i as c u r r en t. n o t e t h a t t h e iout p output s mu s t r e ma in op en fo r pr o p er o p era t ion. 04560-0-065 ioutn? ioutn+ ioutg ? ioutg+ iout_p+ iout_p ? 0 to ? 7.5db 0 to ?12db re fio re fadj r set 0.1 f to load avdd iout pk r r avdd r s 0.1 f r s 0.1 f dual npn phillips pbr951 iamp txdac f i gure 65. v o ltage mode o p er atio n the p e a k dif f er en t i al v o l t a g e sig n al de ve lo p e d acr o s s t h e n p n s bas e s is as fol l o w s: ) ( i n r vout pk ? ? = eq uat i on 4. w h er e: n is t h e ga i n s e t t in g o f t h e p r ima r y mir r o r . i is t h e st an di n g c u r r en t o f t h e txd a c def i ne d in e q u a t i on 1. the co mm on- m o d e b i as v o l t ag e s e en a t io u t n+ and io utn? is a p p r o x im a t e l y a v dd ? v o u t pk , w h i l e t h e c o m m o n - m o d e v o l t a g e s e en a t io ut g+ and io ut g? is a p p r o x ima t e l y t h e np n s v be dr o p b e lo w this le v e l ( a vd d ? v o ut pk ? 0.65). i n t h e v o l t a g e m o de co nf igura t ion, t h e t o t a l p o w e r dis s i p a t e d w i th i n th e i a mp i s a s f o ll o w s : } ) 65 . 0 ( ) {( 2 g vout avdd n voutpk avdd i p pk iamp ? ? ? + ? ? ? ? = eq uat i on 5. the emi t t e rs o f t h e n p n t r an sis t o r s a r e ac-co u ple d t o t h e tra n sf o r m e r 1 v i a a 0.1 f b l o c k i n g c a p a ci t o r a nd s e r i es r e sist o r o f 1? t o 2 ?. n o t e tha t p r o t ec tio n dio d es a r e no t s h own f o r cla r i t y p u r p os es, b u t sh o u ld b e co n s ider e d , if i n t e r f acin g t o a p o we r or phon e l i ne.
ad9866 rev. 0 | page 32 of 48 the am o u n t o f st an di n g and si g n a l -dep e nden t c u r r en t us e d to b i as t h e n p n t r an sis t o r s is dep e n d e n t on t h e p e ak c u r r en t, io u t pk , r e q u ir e d b y t h e lo ad . i f t h e lo ad is va r i ab le, det e r m i n e th e w o r s t ca s e , io u t pk , a n d a d d 3 ma o f ma rg in to en sur e t h a t th e n p n tra n si s t o r s r e m a i n in th e a c ti v e r e gi o n d u ri n g pea k loa d c u r r en ts. th e gain o f t h e s e conda r y p a t h , g, a n d t h e txd a c s s t an din g c u r r en t, i, ca n be s e t usin g the f o l l o w in g eq u a tion: 04560-0-066 i (ma) i su pply (ma) 123 456 78 9 1 0 1 1 1 2 1 3 100 10 20 30 40 50 60 70 80 90 iampn output txdacs avdd i g ma iout pk ? = + 3 eq uat i on 6. the v o l t a g e o u t p u t dr i v er exhib i ts a hig h ou t p ut im p e dan c e , if th e b i a s curr e n ts f o r th e n p n tra n si s t o r s a r e r e m o v e d . t h i s f e at u r e i s a d v a n t a g e o u s i n h a l f - d u p l e x ap p l i c at i o n s ( f o r e x a m p l e , p o w e r lin e s) in whic h t h e tx ou t p u t dr i v er m u s t g o in t o a hig h im p e dan c e sta t e while in rx m o de . i f th e ad98 66 is co nf igur ed fo r t h e ha lf-d u p lex m o de (mode = 0), t h e i a mp , tx d a c, and in t e r p ol a t ion f i lt er a r e a u t o ma t i ca l l y p o w e r e d d o wn a f ter a tx b u rs t (via t x e n ), th us p l acin g th e tx dr i v er in t o a hig h i m p e d a nc e s t a t e w h i l e re d u c i ng i t s p o we r c o nsu m pt i o n . f i gure 66. cur r ent cons umpt ion of t x d a c and ia mp in current mod e o p er at ion wit h io u t n o n ly ( d ef ault i a m p s e t t i ng s ) 04560-0-067 i (ma) i su pply (m a) 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 100 110 120 130 140 150 10 20 30 40 50 60 70 80 90 ioutn output ioutg output txdac avdd iamp curre nt c o ns um pti o n c o ns ider a t io ns the tx p a t h s ana l og c u r r en t co n s um pt io n is an im p o r t a n t co n s idera t ion w h e n det e r m i n ing i t s con t r i b u t i on t o t h e o v era l l o n -ch i p p o w e r dissi p a t io n. t h i s is esp e c i a l ly t h e cas e in f u l l - d u plex a p pli c a t i o n s , w h er e t h e p o w e r dis s i p a t i o n can exce e d t h e maxim u m limi t o f 1.66 w , if th e i a mp s i o ut pk is s e t t o hig h . the a n alog c u r r en t co ns um p t ion i n cl udes t h e txd a c s a n alog s u p p l y (p in 43) alo n g w i t h t h e st a nding c u r r en t f r o m t h e i a mp s o u t p u t s. e q ua tion 2 and e q ua tion 5 c a n be us e d t o calc u l a t e t h e p o w e r dis s i p a t e d i n t h e i a mp fo r t h e c u r r en t and v o l t a g e m o de c o nf igura t io n. f i gur e 66 s h o w s t h e c u r r en t co n s um p t i o n f o r th e t x d a c a n d i a mp a s a fun c ti o n o f th e txd a c s s t an din g c u r r en t, i, w h e n on ly t h e iou t n output s ar e us e d . f i gur e 67 s h o w s t h e c u r r en t co ns um p t io n fo r t h e txd a c a nd i a mp as a f u n c t i on o f t h e txd a c s st an d i n g c u r r en t, i, w h en t h e io u t n an d i o u t g o u t p uts a r e us e d . b o t h f i gur e s a r e w i t h t h e def a u l t c u r r en t mir r o r ga in s e t t in gs o f n = 4 a nd g = 12. f i gure 67. cur r ent cons umpt ion of t x d a c and ia mp in current mod e o p er at ion wit h io u t n o n ly ( d ef ault i a m p s e t t i ng s )
ad9866 rev. 0 | page 33 of 48 receive pa th the r e cei v e p a t h b l o c k dia g ram f o r th e ad98 66 (o r ad9865) is s h own in f i gur e 68. th e r e cei v e sig n al p a th co n s is ts o f a 3-s t a g e rxpga, a 3-p o le p r og ra mma b l e lp f , a nd a 12-b i t (o r 10-b i t) a d c . n o t e tha t th e a d d i ti o n al 2 b i ts o f r e so l u ti o n o f f e r e d b y th e ad9866 (vs. th e ad9865) r e s u l t in a 3 db t o 5 db lo w e r n o is e f l o o r dep e n d in g o n t h e rxpga ga in s e t t i n g an d lpf c u t o f f f r e q uen c y . a l s o w o rk in g i n co n j un c t ion w i t h t h e r e cei v e p a t h is a n o f fs et co r r e c t i o n cir c ui t. th e s e b l o c ks a r e dis c us s e d i n det a i l in t h e fol l o w in g s e c t io n s . n o t e t h a t t h e p o w e r c o n s um pt io n o f t h e rx pg a can b e m o dif i e d v i a re g. 0x 13 as dis c uss e d i n t h e p o w e r c o n t r o l a nd diss i p a t ion s e c t io n. 04560- 0- 068 0 to 6db ? = 1db ?6 to 18db ? = 6db ?6 to 24db ? = 6db xta l rx ? 4 6 10/ 12 register control clk syn. adc 80msps cl k o ut _1 cl k o ut _2 os c i n rx + 2 m clk multiplier 2-pole lpf 1-pole lpf spo r t p g a[ 5: 0] rx cl k rx e n / s y n c a d i o [ 11: 6 ] / t x [5 :0 ] a di o [ 11: 6] / rx [ 5 : 0 ] gain mapping lut spga a d 986 5/a d 9 8 6 6 f i g u re 68. f u nc t i o n al bl ock d i ag r a m o f r x p a t h r x progr a mmable gain am plifie r the rxpga has a dig i t a l l y p r og ra mma b l e ga i n ra n g e f r o m ?12 db t o +48 db wi t h 1 db r e s o l u tio n via a 6 - b i t w o r d . i t s p u r p os e is t o ext e nd t h e d y na mic ra n g e o f t h e rx p a t h s u ch t h a t th e in p u t o f th e a d c i s p r e s en t e d w i t h a si gn al th a t s c ale s wi t h in i t s f i xe d 2 v in p u t s p a n . ther e a r e m u l t i p le wa ys o f s e t t in g t h e rxp g a s gain as dis c us s e d in the r x pga c o n t r o l s e c t io n, as we l l as a n a l t e r n a t iv e 3-b i t ga i n ma pp in g h a v i n g a ra n g e o f ?12 db t o +36 db wi th 8 db r e s o l u tio n . t h e r x p g a i s co m p ri sed o f tw o secti o n s : a c o n t in u o u s ti m e pga (cpga) fo r co urs e ga in and a s w i t ch e d c a p a ci t o r pg a (s pga) f o r f i n e ga in r e s o l u tion. the cpg a co nsis ts o f tw o cas c ade d ga in s t a g es p r o v idin g a ga in ran g e f r o m ?12 db t o +42 db wi th 6 db r e s o l u tio n . the f i rs t s t a g e fe a t ur es a lo w n o is e p r e a m p lif i er (< 3.0 nv/r t h z), t h er eb y e l imina t i n g t h e ne e d fo r a n ext e r n al p r e a m p lif i er . the s p ga p r o v ides a ga in ra n g e f r o m 0 db t o 6 db wi t h 1 db r e s o l u tion. a lo ok-u p tab l e (l ut) is us e d t o s e l e c t t h e ap p r o p r i at e g a i n s e t t i n g f o r e a c h s t a g e . the n o minal di f f er en t i al i n p u t i m p e dance o f t h e rxpga i n p u t a p p e a r in g a t the de vice r x + a nd r x ? in p u t p i n s is 400 ?//4 p f (20%) a nd r e ma in s r e la t i v e l y in d e p e n d e n t o f ga in s e t t i n g. t h e pga in p u t is s e l f -b ias e d a t a 1.3 v co mm o n -m o d e le v e l al lo w- in g maxim u m in p u t v o l t a g e swin gs o f 1.5 v a t r x + an d r x ?. a c co u p lin g t h e in p u t sig n al t o this s t a g e via c o u p lin g c a p a ci - t o r s (0.1 f) is r e co mm en de d to en s u r e t h a t an y ext e r n al dc o f fs et do es n o t get a m plif ie d wi t h hig h rxpga ga in s e t t i n gs, p o t e n t ia l l y exce e d in g t h e ad c in p u t ra n g e . t o limi t t h e rx pga s s e lf- i nd u c e d i n p u t o f fs et, a n o f fs et can c e l l a t i on lo op is in cl ud e d . t h is can c e l la t i o n lo o p is a u to m a t i ca l l y p e r f o r m e d up o n p o w e r - u p an d c a n a l s o b e ini t i a t e d v i a s p i . d u r i n g ca li b r a t io n, t h e rxpga s f i rst st a g e is i n te r n a l ly s h or te d, a n d e a ch g a i n st age s e t to a h i g h g a i n s e t t i n g . a dig i tal s e r v o lo o p s l a v e s a cal i b r a t ion d a c, w h ic h f o r c es th e rx in p u t o f fs et t o b e wi t h in 32 ls b fo r t h is p a r t ic u l a r hig h ga in s e t t in g. al t h o u g h t h e o f fs et va r i es f o r o t h e r ga in s e t t in gs, t h e o f fs et is typ i ca l l y limi te d t o 5% o f t h e ad c s 2 v in pu t s p a n . n o t e th a t th e o f fse t ca n c e l la ti o n ci r c ui tr y i s i n t e n d e d t o r e d u ce t h e v o l t ag e o f fs et a t t r ib ut e d t o onl y t h e rxpga s in p u t st age, not an y d c of f s e t s a t t r i b ut e d to a n e x te r n a l s o u r c e . t h e g a i n of t h e r x p g a s h ou l d b e s e t to m i n i m i z e cl ippi ng of t h e ad c w h i l e u t i l izin g m o s t of i t s d y namic ran g e . th e maxim u m p e a k -t o-p e a k dif f er en t i al v o l t a g e t h a t do es n o t r e s u l t in cli p p i n g o f t h e ad c is sh o w n in f i gur e 69. w h i l e t h e g r a p h sug g ests t h a t maxim u m in pu t s i g n a l fo r a ga in s e t t i n g o f ?12 db is 8.0 v p-p , t h e maxim u m in p u t v o l t a g e i n t o t h e pga sh o u ld b e li mi te d t o less t h a n 6 v p-p to p r e v en t t u r n i n g o n esd prote c t i on d i o d e s . f o r a p pl i c a t i o ns h a v i n g h i g h e r m a x i m u m in p u t sig n als, co n s ider addin g an ext e r n al r e sis t i v e a t t e n u a t o r ne t w or k . wh i l e t h e i n put s e ns i t i v it y of t h e r x p a t h i s d e g r a d e d b y t h e am o u n t o f a t te n u a t ion on a db-to - db b a sis, t h e lo w n o is e cha r ac t e r i st ics of t h e rxpga p r o v ide s o m e desi g n ma rg in such t h a t t h e ext e r n a l lin e n o is e r e ma in s t h e dominan t s o ur ce . 04560-0-069 gain (db) full-s cale p e ak-to-p e ak inp u t s p an (v ) ? 1 2 ? 6 0 6 1 21 82 43 03 64 24 8 8.0000 4.0000 2.0000 1.0000 0.5000 0.2500 0.1250 0.0625 0.0312 0.0156 0.0100 f i g u re 69. m a x i mu m p e ak -t o - p e ak in put v s . r x pg a g a in s e t t i ng t h at d o es not r e s u lt in a d c cl ip p i ng
ad9866 rev. 0 | page 34 of 48 l o w - p a ss fil t er the lo w-p a s s f i l t er (lp f ) p r o v ides a t h ir d o r de r r e s p o n s e wi t h a c u t-o f f f r e q uenc y t h a t is typ i ca l l y p r og ra mma b l e o v er a 15 mh z t o 35 mh z s p an. f i gur e 68 s h o w s tha t t h e f i rs t real p o le is im ple m e n t e d wi t h in t h e f i rst cp ga ga in st a g e , and t h e co m p lex p o le p a ir is im pl em e n t e d i n t h e s e con d c p ga g a in st a g e . c a p a ci t o r a r ra y s a r e us e d t o va r y t h e dif f er en t r - c t i m e co n s ta n t s wi th in th ese tw o s t a g e s i n a ma nn e r t h a t c h a n g e s th e c u t-o f f f r e q uenc y w h i l e p r es er vin g t h e n o r m al ize d f r e q ue n c y r e s p o n s e . b e ca u s e a b s o l u te r e sis t o r a nd c a p a ci t o r val u es a r e p r o c es s-dep e n d en t, a calib r a t ion r o u t in e l a s t ing les s tha n 100 s a u t o ma ticall y occur s ea c h tim e th e t a r g e t cu t - o f f f r eq u e n c y r e g i s t er (reg. 0x08) is u p da t e d , en s u r i n g a r e p e a t a b le c u t-o f f fr e q u e n c y fr o m d e v i c e t o d e v i c e . al th o u g h th e de fa ul t set t in g sp eci f i e s th a t t h e l p f be a c t i v e , i t ca n a l s o b e b y p a ss e d p r o v id in g a n o mina l f ?3 d b o f 55 mh z. t a b l e 20 sh o w s t h e sp i r e g i s t ers p e r t a i ning t o t h e l p f . tab l e 20. spi registers for rx low-pass filter a ddr ess (he x ) bit description 0x07 (0) enable rx lpf 0x08 (7:0) t a r g et va lu e the n o r m a l iz e d wideb a nd ga i n r e sp o n s e is sh ow n in f i gur e 70. the n o r m a l iz e d p a ss-b and ga i n a nd g r o u p dela y r e sp o n s e s a r e s h own in f i gur e 71. th e n o r m al ize d c u t-o f f f r eq uen c y , f ?3 d b , r e su l t s in ?3 d b a t t e n u a t io n. a l s o , t h e ac t u a l g r ou p de l a y t i m e (gdt) r e sp o n s e can b e ca lc u l a t e d g i ve n a p r o g r a mme d c u t-o f f f r eq uen c y usin g th e f o l l o w in g e q ua t i o n : ) 45 . 2 /( 3 db f gdt normalized gdt actual ? ? = 04560-0-070 frequency gain ( d b) 0 5 1.0 3.0 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 2.5 2.0 1.5 0.5 f i gur e 7 0 . lp f? s no rm al iz ed wi deb a nd g a i n resp o n se 04560-0-071 normalized frequency gain ( d b) 0 0.5 1.0 0.9 0.3 0.4 0.8 0.2 0.1 normalize d group de lay tim e r espon se ( g d t ) 1.30 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 0.25 ? 3.00 ? 2.75 ? 2.50 ? 2.25 ? 2.00 ? 1.75 ? 1.50 ? 1.25 ? 1.00 ? 0.75 ? 0.50 ? 0.25 0 0.6 0.7 normalized group delay normalized gain response f i gur e 7 1 . lp f? s no rm al iz ed p a ss -band g a in and g r o u p d e la y resp o n ses the ?3 db c u t-o f f f r eq uen c y , f ?3 d b , is p r og ra m m a b le b y wr i t ing an 8 - bit word, re f e r r e d to a s t h e t a r g e t , t o reg. 0x08. th e c u t-o f f fr e q u e n c y i s a fu n c t i o n o f t h e a d c s a m p l e r a t e , f ad c , a nd to a les s er ext e n t rx pga ga in s e t t ing (in db). f i gure 72 s h o w s h o w th e f r eq uen c y r e s p o n s e , f ? 3 d b , va r i es as a f u n c t i o n o f t h e rxp g a ga in s e t t in g. 04560-0-072 input frequency (mhz) fundame n tal (db) 01 0 5 0 30 25 5 3 ?1 8 ?1 2 ?6 0 15 20 35 40 ?15 ?9 ?3 45 ?6db gain 0db gain +6db gain +18db gain +30db gain +42db gain f i gur e 7 2 . e ffects o f rxp g a g a in on lpf f r eq uenc y response ( f ?3 d b = 3 2 m h z (@ 0 db and f ad c = 80 ms p s ) the fol l o w ing fo r m u l a 1 c a n b e u s e d to e s t i ma te f ?3 d b fo r a rxpga ga in s e t t in g o f 0 db: ) 83 . 23 30 / ( ) 80 / ( ) / 128 ( 0 _ 3 + ? ? = ? adc adc db db f f target f e uat i on f i gur e 73 co m p a r es th e m e as ur ed and calc u l a t e d f ?3 d b usin g t h is fo r m u l a. 1 em pi ri ca lly d e ri v e d f o r a f ?3 d b r a n g e of 15 mh z t o 35 mhz a n d f adc of 40 m s ps t o 80 ms ps wi t h a n r x pga = 0 db .
ad9866 rev. 0 | page 35 of 48 04560-0-073 target-decimal equivalent fre q ue ncy (mhz) 48 128 224 192 96 112 176 80 64 35 15 17 19 21 23 25 27 29 31 33 144 160 208 50 msps calculated 80 msps calculated 50 msps measured 80 msps measured f i g u re 73. m e as ur e d and cal c ul at ed f ?3 db v s . t a r g et v a lu e fo r f ad c = 50 m s ps and 80 m s ps the fol l o w in g s c a l in g fac t o r can b e a pplie d t o t h e p r e v io us for m u l a to c o m p e n s a te for t h e r x p g a g a i n s e tt i n g on f ?3 d b : 382 / ) ( 1 db in rxpga factor scale ? = eq uat i on 9. this s c a l in g fac t o r r e d u ces t h e ca lc u l a t e d f ?3 d b as t h e rxpga is i n c r e a s e d. a p pl i c a t i o ns t h a t ne e d to m a i n t a i n a m i n i m u m c u t - of f f r e q u e nc y , f ?3 d b _min , f o r al l r x pga ga in s e t t in gs s h o u l d f i rs t det e r m i n e t h e s c alin g fac t o r fo r t h e hig h e s t rx pga ga i n s e t t ing t o b e u s e d . n e x t , t h e f ?3 d b _min sho u ld b e divide d b y t h is s c a l e f a c t or to nor m a l i z e to t h e 0 db r x p g a g a i n s e tt i n g ( f ? 3 db _0 db ). eq ua ti o n 8 ca n th en b e used t o calcula t e t h e ta rg e t val u e . t h e l p f f r e q u e nc y re sp ons e s h ow s a sl i g h t s e n s it i v it y to t e m p era t ur e , as sh own i n f i gur e 74. a p plica t ions s e n s i t i v e t o t e m p era t ur e dr i f t ca n r e calib r a t e t h e l p f b y r e wr i t i n g t h e t a rget val u e t o reg. 0x 08. 04560-0-074 target-decimal equivalent fre q ue ncy (mhz) 96 128 240 192 176 112 35 15 20 25 30 144 160 208 f out actual 80mhz and ?40 c 224 f out actual 80mhz and +25 c f out actual 80mhz and +85 c f i g u re 74. t e mpe r a t ur e d r if t of f ?3 d b for f ad c = 8 0 m s ps an d r x pg a = 0 db anal og t o digit a l c o nverter ( a dc ) the ad9866 f e a t ur es a 12 -b i t analog-t o-dig i tal co n v er t e r (ad c ) c a p a b l e o f u p t o 80 ms ps. ref e r r in g t o f i gur e 68, th e ad c is dr i v en b y th e s p g a s t ag e , whic h p e r f o r m s bo t h t h e s a m p l e - a nd - h o l d a n d t h e f i ne g a i n a d j u st f u nc t i ons . a b u f f e r a m plif ier (n ot sh o w n) is ol a t es t h e last cpga g a in st a g e f r o m t h e d y na mic lo ad p r es en t e d b y t h e spga st a g e . the f u l l -s c a le i n p u t s p a n o f th e a d c i s 2 v p - p , w i th th e full - s c a l e i n p u t s p a n in t o t h e s p ga ad j u s t a b le f r o m 1 v t o 2 v in 1 db in cr em en ts, dep e n d in g on th e pg a ga in s e t t in g. a p i p e li n e d m u l t ist a ge a d c a r chi t e c t u r e is us e d t o achi e v e h i g h sa m p le ra t e s while co n s um in g lo w po w e r . t h e a d c d i s t ri b u t e s th e con v ersio n o v er s e v e ral smal ler a/d su bb lo c k s, r e f i nin g t h e co n v ersio n w i t h p r og r e s s i v e l y hig h er acc u rac y as i t p a s s es t h e re su l t s f r om st age to st ag e on e a ch cl o c k e d ge. the a d c typ i cal l y p e r f o r m s bes t w h en dr i v en in t e r n al l y b y a 50% d u ty c y cle clo c k. this is es p e c i al l y t h e cas e w h e n o p e r a t in g t h e ad c a t hig h s a m p le r a t e (55 ms ps t o 80 ms ps) a nd/o r lo w e r in t e r n a l b i as le ve ls, w h ich a d v e rs e l y a f fe c t in t e rst a ge s e t t ling ti m e r e q u i r em en t s . the a d c s a m p l i ng cl o c k p a t h a l s o incl u d es a d u ty c y cl e re store r c i rc u i t , w h i c h e n su re s t h a t t h e a d c ge t s a ne ar 5 0 % d u ty c y cle clo c k e v en w h e n p r es en t e d wi t h a clo c k s o ur ce wi t h p o o r symm etr y (35/65). this cir c ui t sh o u ld be ena b led , if t h e ad c s a m p ling clo c k is a b u f f er e d versio n o f t h e r e fer e n c e s i g n a l ap p e a r i n g at o s c i n ( s e e t h e c l o c k sy nt h e s i z e r s e c t i o n ) a nd if t h is r e fer e n c e sig n a l is de r i ve d f r o m a n o s ci l l a t o r o r cr y s t a l w h os e sp e c if ie d sy m m e t r y ca nn o t b e g u a r a n t e e d t o b e wi t h in 45 /55 (or 55/45). this cir c ui t can r e ma i n dis a b l e d , if t h e ad c s a m p ling clo c k is der i ve d f r o m a divid e d do wn versio n o f th e c l o c k syn t h e sizer s v c o , be c a us e this c l o c k is n e a r 50 %. the ad c s p o wer co n s um p t io n ca n be r e d u ce d b y 25 ma, wi th minimal ef f e c t o n i t s p e r f o r ma n c e , b y s e t t ing b i t 4 o f reg. 0x07. a l t e r n a t i v e p o w e r b i as s e t t in gs a r e als o a v a i lab l e v i a re g. 0x13, as dis c uss e d i n t h e p o w e r c o n t rol a nd dissi p a t i o n s e c t ion. l a st ly , t h e a d c c a n b e c o m p l e tely p o we re d dow n for ha l f - d u p l ex o p era t ion, f u r t h e r r e d u cin g the ad9866 s p e ak p o w e r co n s um p t io n.
ad9866 rev. 0 | page 36 of 48 04560-0-075 1.0v to adcs reft refb c1 0.1 f c2 10 f c3 0.1 f c4 0.1 f c1 c4 c2 c3 top view a g c tim i ng c o nsider a t io ns wh en impl eme n ti ng a di git a l agc t i m i ng lo o p , it is i m po r t a n t to consider th e rx path l a te ncy an d set t li ng ti me of the rx pa th in response to a change in gain setti ng. f i gur e 2 1 an d f i gur e 24 show the rxpg as settling resp onse to a 60 db and 5 db c h ang e i n ga in se tt in g w h en usin g th e t x [5:0] or pga[5:0] port. w h i l e t h e r x pga se tt li n g ti me ma y a l so show a sl ight depe ndency on the lpf s cutoff frequency, the adcs p i pel i ne delay along w i t h the a d io b u s i n terfac e present s a more sig n ifi c ant del a y. th e amou n t of d e l a y or l a te nc y d e p e nd s o n w h e t he r a h a l f - or f u l l - d u p l ex is s e lec t e d . an im p u ls e res p o n s e a t t h e rxpga s in p u t ca n be obs e r v ed a f t e r 10.0 ad c c l o c k c y c l es (1/f ad c ) in t h e c a se o f a ha lf-d u p lex in t e r f ace and 1 0 .5 ad c clo c k c y cles in t h e c a s e o f a f u l l -d u p lex in t e r f ace. this l a t e n c y a l o n g wi t h t h e rxpga s e t t ling tim e sho u ld be con s ide r ed t o en s u r e st a b ili t y o f th e ag c l o o p . f i gure 7 5 . adc ref e r e nc e a n d d e c o up l i n g t h e a d c h a s a n i n te r n a l vo lt a g e re f e re nc e a n d re f e re nc e a m p l i - f i e r a s show n i n f i g u re 7 5 . t h e i n te r n a l b a n d g a p re f e re nc e ge ne r a te s a st a b l e 1 v re fe re nc e l e vel t h a t i s c o n v e r te d to a dif f er en t i al 1 v r e fer e n c e ce n t ere d ab o u t mid-su p p l y (a vd d/2 ) . the o u t p u t s o f t h e dif f er en t i al r e fer e n c e am plif i e r a r e a v a i la b l e a t t h e ref t and ref b p i ns and mu s t b e p r o p e r ly de co u p le d fo r o p t i m u m p e r f o r ma nce . th e re ft an d refb pi n s a r e con v en- ien t l y si t u a t e d a t t h e co r n ers o f t h e c s p p a cka g e s u ch t h a t c1 (0603 typ e ) can be p l ace d dir e c t l y acr o s s i t s p i n s . c3 a nd c4 c a n b e pl ace d under n e a t h c1, and c 2 (10 f t a n t a l u m ) can b e place d f u r t h e st f r o m t h e p a ck age. table 21. spi registers for rx adc a ddr ess (he x ) bit description 0x04 (5) dut y c y cle r e stor e cir c uit (4) adc clock fr om pll 0x 07 (4) adc l o w pow er mode 0x13 (2:0) adc po w e r bi as adjust
ad9866 rev. 0 | page 37 of 48 clock synthesizer the ad9866 g e n e ra t e s al l i t s in t e r n al s a m p lin g c l o c ks, as w e l l as tw o us er -p r o g r a mma b l e clo c k o u t p uts a p p e a r ing a t cl k o ut1 an d c l k o u t 2 , f r om a s i ng l e re f e re nc e so u r c e as s h o w n in f i g u re 7 6 . t h e r e f e re nc e s o ur ce ca n b e e i t h er a f u ndam e n t a l f r eq ue n c y o r a n o v e r t o n e q u a r tz cr ys tal co n n e ct ed bet w een oscin and xt al w i t h t h e p a r a l l el r e s o na n t lo ad com p on e n ts as sp e c if ie d b y t h e cr y s t a l man u fac t ur er . i t ca n a l s o b e a t t l- lev e l c l o c k a p p l ied t o osci n wi th xt al lef t u n co nnec t e d . the da t a r a te, f da t a , f o r th e tx and rx da t a p a ths m u s t al wa ys b e e q ual . th er efo r e , t h e ad c s s a m p le ra te , f ad c , i s a l w a y s e q u a l t o f da t a , while t h e txd a c u p da t e ra t e is a f a c t o r of 1, 2, o r 4 o f f da t a , dep e n d i n g o n t h e in t e r p ol a t io n f a c t o r s e le c t e d . t h e d a t a ra t e r e f e rs t o the w o r d ra te an d s h o u ld n o t b e c o nf us ed wi t h t h e ni bbl e r a te i n f u l l - d upl e x i n te r f a c e. 2 n xt a l c 1 2 l 2 r 2 m clk multiplier c2 xt a l os c i n cl ko ut 2 cl ko ut 1 t o adc t o t x dac 04560- 0- 076 f i gure 76. cl ock o s cil l a to r and s y nthe s i z e r the 2 m c l k m u lt ip l i e r c o nt a i n s a p l l ( w it h i n t e g r a t e d l o op f i lte r ) an d v c o c a p a bl e of ge ne r a t i ng a n output f r e q u e nc y t h a t is a m u l t i p le o f 1, 2, 4, o r 8 o f i t s in p u t r e f e r e n c e f r eq uen c y , f osci n , a p p e ar i n g a t o s c i n . t h e i n put f r e q u e nc y r a nge of f osci n is b e tw e e n 20 mh z an d 80 m h z, w h i l e t h e v c o ca n op era t e o v er a 40 mhz t o 20 0 mh z sp an. f o r t h e b e st ph as e n o is e / j i t t er cha r ac t e r i s t ics, i t is advis a b l e t o o p era t e t h e v c o w i t h a f r e - q u en c y b e tween 100 mh z and 2 00 mh z. the v c o o u t p u t dr i v es t h e tx d a c dir e c t ly such t h a t i t s up da te r a te, f dac , i s rel a te d to f osci n b y th e f o llo w i n g eq ua ti o n : oscin m dac f f ? = 2 eq uat i on 1 0 . w h er e m = 0, 1, 2, o r 3. m is th e pll s m u l t i p lica t i o n f a c t o r s e t in reg. 0x04. th e val u e o f m is det e r m in e d b y the tx p a th s w o r d r a t e , f da t a , a nd dig i t a l in t e r p ol a t ion fa c t o r , f , a s show n i n t h e f o l l ow i n g e q u a t i o n : ) / ( log 2 oscin data f f f m ? = eq uat i on 1 1 . n o te t h a t , i f t h e re f e re nc e f r e q ue n c y a p p e a r in g a t oscin is c h os en t o b e eq ual t o the ad98 66 s tx and rx p a th s w o r d ra t e , th e n m is sim p ly e q ual t o log 2 (f). t h e c l oc k so u r ce f o r th e ad c ca n be s e l e ct ed in re g . 0 x 0 4 a s a bu f f e r e d ve r s i o n of t h e re f e re n c e f r e q u e n c y ap p e a r i n g at o s c i n (defa u l t s e t t in g) o r a divide d ve rsio n o f t h e v c o o u t p ut (f dac ). the f i rst o p t i on is t h e def a u l t s e t t in g an d m o st desir a b l e, if f osci n is e q ual t o t h e ad c s a m p le ra te , f ad c . t h i s o p t i o n t y p i c a l l y r e s u l t s in t h e b e s t ji t t e r/phas e no is e p e r f o r ma nce fo r t h e a d c sa m p l i n g c l oc k . t h e sec o n d o p tio n i s s u i t a b l e in c a se s wh e r e f osci n i s a f a c t or of 2 or 4 l e ss t h an t h e f ad c . i n t h i s c a s e , t h e divider r a t i o , n, is ch o s en such t h a t t h e d i vide d do wn v c o output , f dac , is e q ual t o t h e ad c s a m p le r a t e , as s h own in t h e f o l l ow i n g e q u a t i on : oscin n m dac f f ? = ? ) ( 2 eq uat i on 1 2 . w h er e n = 0, 1, o r 2. f i gur e 77 sh o w s t h e d e g r ad a t ion in ph as e n o is e p e r f o r ma n c e im p a r t e d on t o t h e ad c s s a m p lin g clo c k fo r dif f er en t v c o o u t p u t f r eq uen c ies. i n this c a s e , a 25 mh z, 1 v p-p sinewa v e was us e d to dr i v e o s cin and t h e pll s m an d n fa c t o r w e r e s e lec t e d t o p r o v ide a n f ad c o f 50 mh z fo r a v c o o p era t i n g f r eq uen c y o f 50, 100, a n d 200 m h z. the rxpg a in p u t was dr i v en wi t h a ne a r f u l l -s ca le, 12 .5 mh z i n p u t si g n a l w i t h a ga in s e t t in g o f 0 db . o p era t ing t h e v c o a t t h e hig h e s t p o s s ib le f r e q uen c y r e su l t s in t h e b e st n a r r o w a n d wide b a nd phas e n o i s e ch ar a c te r i st i c s . f o r c o m p ar i s on pu r p o s e s , t h e cl o c k s o u r c e for t h e ad c was t a k e n dir e c t ly f r o m osci n w h e n dr i v en b y a 50 mh z s q ua r e wa v e . 04560-0-077 frequency (mhz) dbfs 2.5 4.5 6.5 8.5 10.5 12.5 14.5 16.5 18.5 20.5 22.5 0 ? 110 ? 100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 direct vco = 50mhz vco = 100mhz vco = 200mhz f i g u re 77. co mp ari s on of p h as e no is e p e r f o r m a nce wh en a d c cl ock s o u r c e is d e rived f r om d i ffer e nt vc o o u tput f r equ e nc ies the cl k sy n t hesizer als o has tw o c l o c k o u t p u t s a p p e a r in g a t clk o ut1 an d clk o ut2. the y a r e p r og ra mma b l e v i a reg. 0x06. b o th o u t p u t s can be in v e r t e d o r dis a bled . th e v o l t a g e le v e l s a p p e a r in g a t t h es e o u t p ut s a r e r e la t i v e t o d r vd d and re m a i n a c t i ve du r i ng a h a rdw a r e or s o f t w a re re s e t . t a bl e 2 2 s h o w s t h e sp i r e g i s t ers p e r t a i ni n g t o t h e clo c k s y n t h e si zer .
ad9866 rev. 0 | page 38 of 48 clkout1 is a divided version of the vco output and can be set to be a submultiple integer of f dac (f dac /2 r , where r = 0, 1, 2, or 3). because this clock is actually derived from the same set of dividers used within the pll core, it is phase-locked to them such that its phase relationship relative to the signal appearing at oscin (or rxclk)can be determined upon power-up. also, this clock has near 50% duty cycle, because it is derived from the vco. as a result, clkout1 should be selected before clkout2 as the primary source for system clock distribution. clkout2 is a divided version of the reference frequency, f oscin , and can be set to be a submultiple integer of f oscin (f oscin /2 l , where l = 0, 1, or 2). with l set to 0, the output of clkout2 is a delayed version of the signal appearing at oscin, exhibiting the same duty cycle characteristics. with l set to 1 or 2, the output of clkout2 is a divided version of the oscin signal, exhibiting a near 50% duty cycle, but without having a deterministic phase relationship relative to clkout1 (or rxclk). table 22. spi registers for clk synthesizer address (hex) bit description 0x04 (4) adc clk from pll (3:2) pll divide factor ( p) (1:0) pll multiplication factor (m ) 0x06 (7:6) clkout2 divide number (5) clkout2 invert (4) clkout2 disable (3:2) clkout1 divide number (1) clkout1 invert (0) clkout1 disable
ad9866 rev. 0 | page 39 of 48 power control and dissipation power-down the ad9866 provides the ability to control the power-on state of various functional blocks. the state of the pwrdwn pin along with the contents of reg. 0x01 and reg. 0x02 allow two user-defined power settings that are pin selectable. the default settings 1 are such that reg. 0x01 has all blocks powered on (all bits 0), while reg. 0x02 has all blocks powered down excluding the pll such that the clock signal remains available at clkout1 and clkout2. when the pwrdwn pin is low, the functional blocks corresponding to the bits in reg. 0x01 are powered down. when the pwrdwn is high, the functional blocks corresponding to the bits in reg. 0x02 are powered down. pwrdwn immediately affects the designated functional blocks with minimum digital delay. table 23. spi registers associated with power-down and half-duplex power savings address (hex) bit description comments 0x01 (7) pll (6) txdac/iamp (5) tx digital (4) ref (3) adc cml (2) adc (1) pga bias (0) rx pga pwrdwn = 0 default setting is all functional blocks powered on. 0x02 (7) pll (6) txdac/iamp (5) tx digital (4) ref (3) adc cml (2) adc (1) pga bias (0) rx pga pwrdwn = 1 default setting is all functional blocks powered off excluding pll. 0x03 (7:3) tx off delay (2) rx pwrdwn via txen (1) enable tx pwrdwn (0) enable rx pwrdwn half-duplex power savings. 1 with mode = 1 and config = 1, reg. 0x02 default settings are with all blocks powered off, with rxclk providing a buffered version of the signal appearing at oscin. this setting results in the lowest power consumption upon power-up while still allowing ad 9865 to generate the system clock via a crystal. half-duplex power savings significant power savings can be realized in applications having a half-duplex protocol allowing only the rx or tx path to be operational at any instance. the power-savings method depends on whether the ad9866 is configured for a full- or half-duplex interface. functional blocks having fast power on/off times for the tx and rx path are controlled by the following bits: txdac/iamp, tx digital, adc, and rxpga. in the case of a full-duplex digital interface (mode = 1), one can set reg. 0x01 to 0x60 and reg. 0x02 to 0x05 (or vice versa) such that the ad9866s tx and rx path are never powered on simultaneously. the pwrdwn pin can then be used to control what path is powered on, depending on the burst type. during a tx burst, the rx paths pga and adc blocks can typically be powered down within 100 ns, while the tx paths dac, iamp, and digital filter blocks are powered up within 0.5 s. for an rx burst, the tx paths can be powered down within 100 ns, while the rx circuitry is powered up within 2 s. the txquiet pin can also be used with the full-duplex interface to quickly power down the iamp and disable the interpolation filter by setting this pin low. this is meant to maintain backward compatibility with the ad9875/ad9876 mxfes with the exception that the txdac remains powered if its ioutp outputs are used. in most applications, the interpola- tion filter needs to be flushed with 0s before or after being powered down. this ensures that, upon power-up, the txdac (and iamp) have a negligible differential dc offset, thus preventing spectral splatter due to an impulse transient. applications using a half-duplex interface (mode = 0) can benefit from an additional power savings feature made available in reg. 0x03. this register is effective only for a half-duplex interface. besides providing power savings for half-duplex applications, this feature allows the ad9866 to be used in applications that need only its rx (or tx) path functionality through pin-strapping, making a serial port interface (spi) optional. this feature also allows the pwrdwn pin to retain its default function as a master power control, as defined in table 10. the default settings for reg. 0x03 provide fast power control of the functional blocks in the tx and rx signal paths (outlined above) using the txen pin. the txdac still remains powered on in this mode, while the iamp is powered down. significant current savings are typically realized when the iamp is powered down. for a tx burst, the falling edge of txen is used to generate an internal delayed signal for powering down the tx circuitry. upon receipt of this signal, power-down of the tx circuitry occurs within 100 ns. the user-programmable delay for the tx
ad9866 rev. 0 | page 40 of 48 pa th po w e r - d o wn i s m e a n t t o m a t c h th e p i pe lin e de la y o f th e las t tx b u rs t s a m p le s u c h tha t p o w e r - do wn o f th e txd a c and i a mp do es n o t im p a c t i t s t r a n s m issio n . a 5 - b i t f i e l d in re g. 0x03 s e ts th e dela y f r o m 0 t o 31 t x cl k c l o c k c y c l es, wi th t h e defa u l t b e in g 31 (0.62 s wi t h f tx cl k = 50 ms ps). th e dig i tal in t e r p ol a t ion f i lt er is a u t o ma t i c a l l y f l ush e d wi t h mids ca le s a m p les p r io r t o p o w e r - do w n , if t h e clo c k sig n a l in t o t h e t x cl k p i n is pr es en t fo r 33 addi t i o n al clo c k c y cles a f t e r tx e n r e t u r n s lo w . f o r a n rx b u rst, the r i sin g edg e o f t x e n is us ed to g e n e r a t e an in t e r n al sig n al (wi t h n o de l a y) tha t p o w e rs u p th e tx cir c ui tr y wi t h in 0.5 s. the rx p a t h p o w e r - o n /p o w er - o f f ca n b e co n t rol l e d b y ei t h er t x e n o r r x e n b y s e t t in g b i t 2 o f reg. 0x03. i n the def a u l t se t t in g, t h e fallin g ed g e o f t x en po w e r s u p th e rx ci r c ui tr y wi t h in 2 s , w h i l e t h e r i sin g e d ge o f t x e n p o wers do wn t h e rx cir c ui tr y wi thin 0.5 s. i f r x e n is s e lec t e d as t h e co n t r o l sig n al , th en i t s r i sin g e d g e p o w e rs u p th e rx cir c ui tr y a nd t h e fal l in g edg e p o w e rs i t do wn. i t is p o s s ib le t o dis a b l e t h e fas t p o w e r - d o w n of t h e t x an d / or r x c i rc u i t r y by s e tt i n g b i t 1 a n d / or bit 0 to 0 . po wer reduc t ion options the p o w e r co n s um p t ion o f th e ad9866 can be sig n if ica n tl y r e d u ce d f r o m i t s defa u l t s e t t in g b y o p t i miz i n g t h e p o w e r c o nsu m pt i o n ve r s u s p e r f o r m a n c e of t h e v a r i ou s f u nc t i on a l b l o c ks in t h e tx a nd rx sig n al p a th. on t h e tx p a th, minim u m p o w e r co n s um pt io n is r e a l i z e d w h en t h e txd a c o u t p ut is us e d dir e c t ly a nd i t s st an di n g c u r r en t, i, is r e d u ce d to as lo w as 1 m a . a l t h o u g h a s l i g ht d e g r a d at i o n i n t h d p e r f o r m a n c e r e s u l t s at r e d u ce d st an d i ng c u r r en ts, i t o f ten r e ma i n s ade q ua te fo r m o st a p plic a t ion s , b e ca us e t h e o p am p dr i v er typ i cal l y limi ts t h e ove r a l l l i ne ar it y p e r f or m a nc e of t h e t x p a t h . t h e l o a d re s i stor s us e d a t t h e tx d a c o u t p uts ( i ou tp+ an d iou t p? ) can b e i n c r e a s e d to ge ne r a te a n a d e q u a te di f f e r e n t i a l v o lt age t h a t c a n b e f u r t h e r am pl if ie d vi a a p o w e r ef f i cien t o p a m p b a s e d dr i v er so l u ti o n . f i gur e 78 s h o w s h o w th e su p p l y curr e n t f o r th e txd a c (p in 43 ) is r e d u ced f r o m 55 ma t o 14 ma as t h e s t an din g c u r r en t is r e d u ce d f r o m 12.5 ma t o 1. 25 ma. f u r t h e r tx p o w e r s a vings ca n be achieved b y b y p a s s in g o r r e d u cin g the i n te r p o l a t i o n f a c t or of t h e d i g i t a l f i lte r a s s h ow n i n fi g u re 7 9 . 04560-0-078 i standing (ma) iavdd txdac (ma) 012 3456 789 1 0 1 1 1 2 1 3 55 10 15 20 25 30 35 40 45 50 f i gure 78. reduc t ion in t x d a c s sup p l y c u rrent vs. stand i ng c u r r ent 04560-0-079 input data rate (msps) i dvdd (m a) 20 30 40 50 60 70 80 55 60 65 15 20 25 30 35 40 45 50 2 interpolation 4 interpolation 1 (half-duplex only) f i gure 79. d i g i tal s u p p ly c u rrent c o nsumption vs. input d a t a rate (dvdd = dr vdd = 3 .3 v and f ou t = f da t a /1 0) p o w e r co n s um p t io n o n t h e rx p a th ca n be ac hie v ed b y r e d u c- in g t h e b i a s le vels o f t h e va r i o u s a m plif iers co n t a i ne d w i t h i n t h e r x p g a a n d a d c . a s pr e v i o u sly note d, t h e r x p g a c o ns i s t s of tw o cpg a a m plif iers a n d one spga am plif ier . the b i a s le v e l s of e a ch of t h e s e am pl i f i e r s a l ong w i t h t h e a d c c a n b e c o n - tr ol led via reg. 0x13 as s h own in t a b l e 24. the defa u l t s e t t in g f o r 0x13 is 0x00 . table 24. spi r e gister for rxp g a and adc b i asing a ddr ess (he x ) bit description 0x07 (4) adc lo w pow er 0x13 (7:5) cpga bias adjust (4:3) spga bias adj u st (2:0) adc po w e r bias adj u s t
ad9866 rev. 0 | page 41 of 48 b e ca us e t h e cp ga p r o c es s e s si g n als in t h e co n t in uo us t i m e do ma i n , i t s p e r f o r ma n c e versus b i as s e t t ing r e ma in s m o st ly indep e n d en t o f t h e s a m p le ra t e . t a b l e 25 sh o w s h o w t h e typical c u r r en t co n s um p t io n s e en a t a v d d (p in s 35 and 40) va r i es as a f u n c t i on o f bi ts (7:5), w h i l e t h e r e ma inin g b i ts ar e ma in t a i n e d a t t h eir def a u l t s e t t in g o f 0. on ly fo ur o f t h e p o ssib le s e t t in gs r e su l t in an y r e d u c t ion in c u r r en t consum p t ion r e l a t i v e t o t h e defa u l t s e t t i n g. re d u cing t h e b i as le vel t y p i ca l l y r e su l t s i n a d e g r ad a t ion in t h e thd v e rs us f r eq uen c y p e r f o r ma n c e as sh o w n in f i gur e 80 d u e to a r e d u c t io n o f t h e am plif ier s uni t y ga i n ba n d w id th , w h i l e th e s n r pe rf o r m a n c e r e m a in s r e la ti v e l y una f f e c t ed . 04560-0-080 cpga bias setting-bits (7:5) s nr (dbfs ) thd (dbc ) 000 100 010 011 001 65.0 40.0 ?20 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 ?25 42.5 45.0 47.5 50.0 52.5 55.0 57.5 60.0 62.5 snr_rxpga = 0db snr_rxpga = 36db thd_rxpga = 0db thd_rxpga = 36db f i g u re 80. th d v s . f in p e r f or m a nce a n d r x pg a bias s e t t i ng s (00 0 ,0 0 1 ,0 10 ,1 00 wit h r x pg a = 0 an d +3 6 db and a i n = ?1 dbfs, l p f s e t t o 26 m h z and f ad c = 50 msp s ) table 25. a n alog suppl y curr en t v s . cpga b i as settin g s at f adc = 65 msps bit 7 bit 6 bit 5 ? ma 0 0 0 0 0 0 1 ? 2 7 0 1 0 ? 4 2 0 1 1 ? 5 1 1 0 0 ? 5 5 1 0 1 2 7 1 1 0 6 9 1 1 1 2 7 the s p g a is i m plem e n t e d as a sw i t ch e d c a p a ci t o r a m plif ier . the r e f ore, i t s p e r f o r manc e ve rs u s b i a s l e vel i s mo st ly de p e nde n t o n t h e s a m p le ra t e . f i gur e 81 sho w s h o w t h e ty p i cal c u r r en t co n s um p t io n s e en a t a v dd (p in s 35 an d 40) va r i es as a f u n c tio n o f b i ts (4:3) a n d s a m p le ra t e , while t h e r e ma inin g b i ts a r e ma in ta in e d a t t h eir def a u l t s e t t in g o f 0. f i gur e 81 s h o w s h o w t h e snr a nd thd p e r f o r ma n c e is a f fe c t e d fo r a 10 mh z si n e wa v e in p u t as t h e ad c s a m p l e ra t e is s w ep t f r om 20 mh z t o 8 0 mh z. 04560-0-081 adc sample rate (msps) i avdd (ma) 20 30 40 50 60 70 80 210 170 175 180 185 190 195 200 205 01 00 10 11 f i gure 8 1 . a v dd c u rr ent vs . sp g a bia s setti ng a n d sam p le r a t e 04560-0-082 sample rate (msps) s nr (dbc ) thd (dbc ) 20 80 30 70 40 50 60 65 55 ?54 ?74 ?72 ?70 ?68 ?66 ?64 ?62 ?60 ?58 ?56 56 57 58 59 60 61 62 63 64 snr-00 snr-01 snr-10 snr-11 thd-00 thd-01 thd-10 thd-11 f i g u re 82. snr and thd p e r f o r man c e v s . f ad c a n d sp g a bia s setting wi th rxp g a = 0 db , f in = 10 mh z. ain = ? 1 dbfs t h e ad c i s b a s e d o n a p i pe lin e a r c h i t ec t u r e w i th ea c h s t a g e co n s ist i n g o f a s w i t ch e d c a p a ci to r a m plif ier . ther efo r e , i t s p e r f or manc e ve rsu s b i as l e vel i s a l s o mo st ly de p e nde n t on t h e s a m p le ra t e . f i g u r e 83 s h o w s h o w the typ i cal c u r r en t co n s um p - tio n s een a t a v d d (p in s 35 and 40) va r i es as a f u n c tion o f b i ts (2:0) a n d s a m p l e ra t e , w h i l e t h e r e ma inin g b i ts ar e ma in t a i n e d a t t h eir def a u l t s e t t in g o f 0. s e t t in g b i t 4 o r reg. 0x07 co r r e- s p on ds t o t h e 0 11 s e t t in g, and t h e s e t t in gs o f 101 a nd 111 r e s u l t in hig h er c u r r en t co ns um p t io n. f i gur e 84 s h o w s h o w t h e snr an d t h d p e r f o r m a nc e are af fe c t e d for a 1 0 m h z s i ne w a v e in p u t f o r th e lo w e r p o w e r set t in gs as the ad c sa m p le ra t e is sw ep t f r o m 20 mh z t o 80 mh z.
ad9866 rev. 0 | page 42 of 48 04560-0-083 sample rate (msps) iav dd (ma) 20 30 40 50 60 70 80 220 120 130 140 150 160 170 180 190 200 210 000 001 010 011 100 101 101 or 111 f i gure 8 3 . a v dd c u rr ent vs . adc bia s s e tti ng a n d s a m p l e r a t e 04560-0-084 sample rate (msps) s nr (dbc ) thd (dbc ) 20 80 30 70 40 50 60 65 55 ?54 ?74 ?72 ?70 ?68 ?66 ?64 ?62 ?60 ?58 ?56 56 57 58 59 60 61 62 63 64 thd-000 thd-001 thd-010 thd-011 thd-100 thd-101 snr-000 snr-001 snr-010 snr-011 snr-100 snr-101 f i g u re 84. snr and thd p e r f o r man c e v s . f ad c a n d sp g a bia s setting wi th rxp g a = 0 db , f in = 1 0 mhz , ai n = ?1 db fs a sine w a ve i n pu t is a st anda r d a nd con v eni e n t m e t h o d o f a n al yzin g t h e p e r f o r ma n c e o f a sys t em. h o w e ver , t h e am o u n t o f p o w e r r e d u c t io n t h a t is p o ssib le is a p pli c a t ion dep e n d e n t, b a s e d o n t h e na t u r e o f t h e i n p u t wa vefo r m (s uch as f r e q uen c y co n t en t, p e a k - t o - r m s ra t i o ) , t h e min i m u m a d c s a m p le, a nd t h e mi ni- m u m ac cep t ab l e le vel o f p e r f o r ma nce. a s a r e su l t , i t is a d vis a b l e t h at p o w e r- s e n s i t i v e ap p l i c at i o n s o p t i m i z e t h e p o w e r b i a s se t t in g o f th e rx pa th usi n g a n i n p u t w a v e f o rm th a t i s r e p r e - s e n t a t i v e o f t h e a p plic a t ion. po wer diss ip a t ion the p o w e r dis s i p a t io n o f t h e ad9866 can b e com e q u i t e hig h in f u l l -d u p lex a p pl ica t ion s i n w h ich t h e tx and rx p a t h s a r e sim u l t an e o usly o p era t i n g wi t h n o m i na l p o w e r b i as s e t t i n gs. i n fac t , s o me a p p l ica t ion s desir i n g t o us e th e i a m p ma y nee d t o e i th e r r e d u c e i t s peak po w e r ca p a b i l i ti e s o r r e d u c e th e po w e r co n s um p t i o n o f th e r x pa t h , so th a t t h e de v i ce s m a xi m u m allo w a b l e po w e r co n s um p t i o n , p max , i s n o t e x ceed ed . p max is s p e c if ie d a t 1 . 66 w t o e n s u r e t h a t t h e die t e m p era t ur e do es n o t exceed 125 o c a t an am b i e n t t e m p er a t u r e o f 85 o c. this sp e c if ic a t ion is b a s e d o n t h e 64 -p in lfscp ha v i n g a t h er ma l re s i st anc e , ja , o f 2 4 o c / w w i t h it s he a t slu g s o l d e r e d . ( t he ja is 30.8 o c/w , if t h e h e a t s l ug r e main s un s o lder ed .) i f a p a r t ic u l a r ap p l i c at i o n s m a x i mu m a m b i e n t t e mp e r a t u r e , t a , f a l l s b e l o w 85 o c, t h e max i m u m a l lo wa b l e p o w e r dissi p a t i o n can b e de ter - mi n e d b y t h e fol l o w in g e q u a t i on: 24 / ) 85 ( 66 . 1 a max t p ? + = eq uat i on 1 3 . a s s u min g t h a t t h e i a mp s comm on- m o d e b i as v o l t a g e is o p era t in g o f f the s a m e a n alog su p p l y as th e ad9866, th e f o l l ow i n g e q u a t i on c a n b e u s e d t o c a l c u l a t e t h e m a x i m u m tot a l cu rr e n t c o n s u m p t i o n , i max , o f t h e i c : 47 . 3 / ) ( iamp max max p p i ? = eq uat i on 1 4 . w i t h an am b i en t t e m p era t ur e o f u p t o 85c, i ma x is 478 ma. i f t h e i a mp is op era t i n g o f f a di f f er en t s u p p l y o r in t h e v o l t a g e m o d e co nf igur a t io n, f i rst ca lc u l a t e t h e p o w e r dissi p a t e d i n t h e ia m p , p ia m p , usi n g eq ua ti o n 2 o r eq ua ti o n 5, a n d th en r e calcu- la te i max , usin g t h e fol l o w in g e q ua t i on: 47 . 3 / ) ( iamp max max p p i ? = eq uat i on 1 5 . f i gur e 78, f i gur e 79, f i gur e 81, a nd f i gur e 83 c a n be us ed t o calc u l a t e t h e c u r r en t co n s um p t io n o f t h e rx and tx p a t h s fo r a gi v e n set t in g . mode sele c t upon power-up and rese t the ad9866 p o w e r - u p s t a t e is det e r m in e d b y th e log i c lev e l s a p p e a r in g a t t h e mode a n d c o nf i g p i ns. t h e mode p i n is us e d t o s e le c t a half- o r f u l l -d u p lex in t e r f ace b y p i n s t r a p p in g i t l o w o r h i gh , r e s p ecti v e l y . t h e c o n f i g p i n i s used in co n j un c - t i o n wi t h t h e mo d e p i n t o deter m in e t h e defa u l t s e t t in gs fo r t h e sp i r e g i s t ers as o u t l i n e d in t a b l e 10. the i n t e n t o f t h es e p a r t ic u l a r defa u l t s e t t i n gs is t o al lo w s o m e a p plic a t ion s t o a v o i d usin g t h e s p i (dis a b le d b y p i n- st ra pp in g se n hig h ), t h er eb y r e d u cin g t h e im plem e n t a t i o n c o s t . f o r ex a m ple, s e t t in g mode lo w a nd c o nf ig hig h co nf igur es t h e ad9866 t o be b a c k wa rd co m p a t i b le wi th t h e ad9975, while s e t t i n g mode hig h and c o nf i g lo w ma k e s i t b a ck w a r d co m p a t i b le wi th th e ad9875. o t h e r a p p l ic a t io ns m u s t us e t h e s p i t o co nf igur e th e de vice . a h a rdw a re ( res e t pi n ) or s o f t w a re (b i t 5 o f reg. 0x00) r e s e t ca n be us e d t o place t h e ad986 6 in t o a k n own s t a t e o f o p era - ti o n a s de t e rm in e d b y th e s t a t e o f th e m o d e a n d co n f i g p i n s . a dc o f fs et ca lib r a t ion and f i l t er t u ni n g r o u t ine is a l s o i n it i a te d up o n a h a rdw a re re s e t , but not w i t h a s o f t w a re re s e t . n e i t he r re s e t m e t h o d f l u s he s t h e d i g i t a l i n te r p o l a t i o n f i lte r s i n th e t x pa th . r e f e r t o th e h a lf- d u p le x m o d e a n d f u ll- d u p le x m o de s e c t ion s fo r info r m a t io n o n f l ushin g t h e dig i t a l f i l t ers.
ad9866 rev. 0 | page 43 of 48 a hardware reset can be triggered by pulsing the reset pin low for a minimum of 50 ns. the spi registers are instantly reset to their default settings upon reset going low, while the dc offset calibration and filter tuning routine is initiated upon reset returning high. to ensure sufficient power-on time of the various functional blocks, reset returning high should occur no less than 10 ms upon power-up. if a digital reset signal from a microprocessor reset circuit (such as adm1818) is not available, a simple r-c network referenced to dvdd can be used to hold reset low for approximately 10 ms upon power-up. analog and digital loop-back test modes the ad9866 features analog and digital loop-back capabilities that can assist in system debug and final test. analog loop-back routes the digital output of the adc back into the tx data path prior to the interpolation filters such that the rx input signal can be monitored at the output of the txdac or iamp. as a result, the analog loop-back feature can be used for a half- or full-duplex interface, to allow testing of the functionality of the entire ic (excluding the digital data interface). for example, the user can configure the ad9866 with similar settings as the target system, inject an input signal (sinusoidal waveform) into the rx input, and monitor the quality of the reconstructed output from the txdac or iamp to ensure a minimum level of performance. in this test, the user can also exercise the rxpga as well as validate the attenuation charac- teristics of the rxlpf. note that the rxpga gain setting should be selected such that the input does not result in clipping of the adc. digital loop-back can be used to test the full-duplex digital interface of the ad9866. in this test, data appearing on the tx[5:0] port is routed back to the rx[5:0] port, thereby confirming proper bus operation. the rx port can also be three-stated for half- and full-duplex interfaces. table 26. spi registers for test modes address (hex) bit description 0x0d (7) analog loop-back (6) digital loop-back (5) rx port three-state
ad9866 rev. 0 | page 44 of 48 pcb design considerations although the ad9866 is a mixed-signal device, the part should be treated as an analog component. the on-chip digital cir- cuitry has been specially designed to minimize the impact of its digital switching noise on the mxfes analog performance. to achieve the best performance, the power, grounding, and layout recommendations in this section should be followed. assembly instructions for the mi cro-lead frame package can be found in an application note from amkor at: http://www.amkor.com/products /notes_papers/mlf_appnote _0902.pdf. component placement if the three following guidelin es of component placement are followed, chances for getting the best performance from the mxfe are greatly increased. firs t, manage the path of return currents flowing in the ground plane so that high frequency switching currents from the digital circuits do not flow on the ground plane under the mxfe or analog circuits. second, keep noisy digital signal paths and sensitive receive signal paths as short as possible. third, keep digital (noise generating) and analog (noise susceptible) circuits as far away from each other as possible. to best manage the return currents, pure digital circuits that generate high switching currents should be closest to the power supply entry. this keeps the highest frequency return current paths short and prevents them from traveling over the sensitive mxfe and analog portions of the ground plane. also, these circuits should be generously bypassed at each device, which further reduces the high frequency ground currents. the mxfe should be placed adjacent to the digital circuits, such that the ground return currents from the digital sections do not flow in the ground plane under the mxfe. the ad9866 has several pins that ar e used to decouple sensitive internal nodes. these pins are refio, refb, and reft. the decoupling capacitors connected to these points should have low esr and esl. these capacitors should be placed as close to the mxfe as possible (see figure 75) and be connected directly to the analog ground plane. the resistor connected to the refadj pin should also be placed close to the device and connected directly to the analog ground plane. power planes and decoupling while the ad9866 evaluation board demonstrates a very good power supply distribution and decoupling strategy, it can be further simplified for many ap plications. the board has four layers: two signal layers, on e ground plane, and one power plane. while the power plane on the evaluation board is split into multiple analog and digi tal subsections, a permissible alternative would be to ha ve avdd and clkvdd share the same analog 3.3 v power plane. a separate analog plane/supply may be allocated to the iamp, if its supply voltage differs from the 3.3 v required by avdd and clkvdd. on the digital side, dvdd and drvdd can share the same 3.3 v digital power plane. this digital power plane brings the current used to power the digital portion of th e mxfe and its output drivers. this digital plane should be ke pt from going underneath the analog components. the analog and digital power planes allocated to the mxfe may be fed from the same low noise voltage source; however, they should be decoupled from each other to prevent the noise generated in the digital portion of the mxfe from corrupting the avdd supply. this can be done by using ferrite beads between the voltage source an d the respective analog and digital power planes with a low esr, bulk decoupling capacitor on the mxfe side of the ferrite. each of the mxfes supply pins (avdd, clkvdd, dvdd, and drvdd) should also have a dedicated low esr, esl decoupling capacitors. the decoupling capacitors should be placed as close to the mxfe supply pins as possible. ground planes the ad9866 evaluation board uses a single serrated ground plane to help prevent any high frequency digital ground currents from coupling over to the analog portion of the ground plane. the digital currents affiliated with the high speed data bus interface (pins 1C16) have the highest potential of generating problematic high frequency noise. a ground serration that contains these cu rrents should reduce the effects of this potential noise source. the ground plane directly unde rneath the mxfe should be continuous and uniform. th e 64-lead lfcsp package is designed to provide excellent thermal conductivity. this is partly achieved by incorporating an exposed die paddle on the bottom surface of the package. however, to take full advantage of this feature, the pcb must have features to effectively conduct heat away from the package. this can be achieved by incorporating thermal pad and thermal vias on the pcb. while a thermal pad provides a solderable surface on the top surface of the pcb (to solder the package die paddle on the board), thermal vias are needed to provide a thermal path to inner and/or bottom layers of the pcb to remove the heat. lastly, all ground connections should be made as short as possible. this results in the lo west impedance return paths and the quietest ground connections. signal routing the digital rx and tx signal path s should be kept as short as possible. also, the impedance of these traces should have a controlled characteristic impedance of about 50 ? . this prevents poor signal integrity and the high currents that can
ad9866 rev. 0 | page 45 of 48 occur during undershoot or oversh oot caused by ringing. if the signal traces cannot be kept shorter than about 1.5 inches, series termination resistors (33 ? to 47 ?) should be placed close to all digital signal sources. it is a good idea to series- terminate all clock signals at their source, regardless of trace length. the receive rx+ and rx? signals are the most sensitive signals on the entire board. careful routing of these signals is essential for good receive path performance. the rx+ and rx? signals form a differential pair and should be routed together as a pair. by keeping the traces adjacent to each other, noise coupled onto the signals appears as common mode and is largely rejected by the mxfe receive input. keeping the driving point impedance of the receive signal low and placing any low-pass filtering of the signals close to the mxfe further reduces the possibility of noise corrupting these signals.
ad9866 rev. 0 | page 46 of 48 evaluation board an evaluation board is available for the ad9865 and ad9866. the digital interface to the evaluation board can be configured for a half- or full-duplex interface. two 40-pin and one 26-pin male right angle headers (0.100 inches) provide easy interfacing to test equipment such as digital data capture boards, pattern generators, or custom digital evaluation boards (fpga, dsp, or asic). the reference clock source can originate from an external generator, crystal oscillator, or crystal. software and an interface cable are included to allow for programming of the spi registers via a pc. the analog interface on the evaluation board provides a full analog front-end reference design for power line applications. it includes a power line socket, line transformer, protection diodes, and passive filtering components. an auxiliary path allows independent monitoring of the ac power line. the evaluation board allows complete optimization of power line reference designs based around the ad9865 or ad9866. alternatively, the evaluation board allows independent evaluation of the txdac, iamp, and rx paths via sma connectors. the iamp can be easily configured for a voltage or current mode interface via jumper settings. the txdacs performance can be evaluated directly or via an optional dual op amp driver stage. the rx path includes a transformer and termination resistor, allowing for a calibrated differential input signal to be injected into its front end. more information on the ad9866 evaluation board can be found at: http://www.analog.com/analog_root/productpage/ producthome/0%2c2121%2cad9866%2c00.html.
ad9866 rev. 0 | page 47 of 48 outline dimensions 1 64 16 17 49 48 32 33 0.45 0.40 0.35 0.60 max 0.60 max 0 . 2 5 mi n 0.50 bsc 0. 2 0 r e f * compliant to jedec standards mo-220-vmmd except for exposed pad dimension bottom view 0.30 0.25 0.18 7. 50 re f 7.25 7.10 sq* 6.95 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 0.05 max 0.02 nom seating plane top view 9.00 bsc sq 8.75 bsc sq pin 1 indicator pin 1 indicator f i gure 85. 6 4 -l ead l e ad f r a m e ch ip s c a l e p a ck ag e (lfcs p ) [c p - 6 4 - 3 ] di me nsio ns sho w n i n mi ll im e t e r s ordering guide model t e mper a t ur e r a nge p a ck age descri ption p a ck age o p tion ad9866bcp ?40c to +85c 64-l e ad lfcsp cp -64-3 ad9866bcprl ?40c to +85c 64-l e ad lfcsp cp -64-3 ad9866chips ?40c to +85c chip AD9866-EB 25c e v alua tion boar d
rev. 0 | page 48 of 48 notes ? 2003 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . c04560C0 C 11/03(0)

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